October 9, 1997

Interface connects ISA bus to µP

Tom Balph, Motorola Semiconductor Products, Tempe, AZ

ICs that interface directly into an ISA-bus structure can provide useful functional extensions to the M68300 family of processors that have a CPU32-style external bus, such as the 68332, 68340, 68341, and 68360 (Figure 1). The bus-interface logic can fit into a 22V10-type PAL or PLD, depending on the system's address-decode and chip-select requirements, as long as DMA is unnecessary. (Click here to download the file from DI-SIG, #2090.)

The bus-interface-logic block generates the required signals and timing to interface the 68K-bus control into the ISA-bus control. Timing generation is based on a nominal 8-MHz system clock that the controller also uses. This block generates the active-low ISA command lines MEMRN, MEMWN, IORN, and IOWN. In turn, the ISA signals IOCS16N (active low), MEMCS16N (active low), and IOCHRDY (active high) are inputs to the logic block. These ISA signals return the appropriate DSACK signals and stretch the access cycle as needed. You can design the interface logic as a state machine or as a serial shift register with a nominal timebase of 125 nsec (8-MHz clock period).

For the ISA-to-68K-interface translation, you need to consider differences in bus-byte ordering and whether to use 68K dynamic bus sizing. Also, the ISA bus uses separate I/O and memory accesses. Another consideration is that the ISA bus is basically a nonhandshake bus, whereas the 68K uses the DSACK handshake. Also, the interface does not support the 68K read-modify-write cycle.

Both the 68K and ISA buses are asynchronous. However, in normal operation, the 68K bus expects handshake signals (DSACK0 and DSACK1) to complete the cycle, whereas the ISA bus normally uses a predetermined cycle time (depending on cycle type and bus width), and the bus "stretches" if the peripheral needs a longer access time.

The ISA bus supports 24 address lines for memory accesses and 16 address lines for I/O accesses, although A₁₆ must go to zero during an I/O access. For both cases, you should include the upper 68K address lines in the address decode. Two signals that route between the address-decode and bus-interface-logic blocks enable mapping of an I/O access into one area of the 68K address map (IO_SPN) and mapping of a memory access into a second area of the 68K map (MEM_SPN) (Figure 1). If you use an integrated µP, such as the 68331 or 68340, programmed chip selects can replace the address-decode logic.

The external bus interface common to the 68300 series is either a 32-bit or a 16-bit data bus and supports bus sizing. When interfacing into a 16-bit ISA-bus interface, you must consider byte ordering and bus sizing. With byte ordering, you encounter the little-endian (ISA) vs big-endian (68K) problem. Simple byte-lane swapping solves this problem by tying the upper ISA-bus [D15:D8] byte to the corresponding lower 68K byte and tying the lower ISA-bus [D7:D0] byte to the corresponding upper 68K byte, respectively. For all accesses, this option works if you properly handle the DSACK signals.

The width of the 683XX-series bus also affects the byte-lane swapping. For an external 16-bit data bus, you can merely swap the byte lanes. For a 32-bit external bus, you wire the lower ISA-bus byte lane to the most significant 683XX byte lane [D31:D24] and wire the upper ISA-bus byte lane to the next most significant byte [D23:D16]. Signal decoding from the 683XX interface to the ISA-type interface, including the DSACK signal responses, is necessary for the simple byte swapping to properly function.

The ISA bus normally holds only address lines A₂₃ through A₁₇ stable at the beginning of the cycle and therefore latches these lines onboard the chip. All address lines on the 68K bus are stable for the cycle, so latching is unnecessary, and the interface circuitry ties the ISA-bus latch signal, BALE, high. The ISA-bus signal, AEN, disables I/O resources during a DMA cycle. You normally tie this signal low when the design doesn't need to support DMA. The SIZ0 signal directly drives SBHEN.

The data bus's Data-In Valid time also requires some special attention. On a memory- or I/O-read cycle in which the cycle has stretched (IOCHRDY was not always active), you must check the data-setup time to the 68K bus. The user must ensure that the design meets the Data-In Valid time with respect to DSACKXN handshake signals. If the Data-In Valid time is too long after the assertion of DSACKXN, you must then delay the DSACK signals (usually by one clock) to allow the data to settle.

Although the ISA bus supports several command-cycle times, depending on the access type and data width, this interface timing is based on a standard cycle time of two clocks or 250 nsec. As a result of this design approach, the ZEROWSN signal from the controller remains unused.

Finally, ISA-bus interrupt requests are normally active high, and, therefore, you need to invert these signals for the 68K environment. The ISA-bus peripherals cannot support a 68K IACK cycle, so you should use autovectored interrupts. Also, be sure to configure the device's IRQ line for level mode to be compatible with 68K requirements. (DI #2090)

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