October 23, 1997

CPCI passes potholes, enters the on-ramp

RICHARD A QUINNELL, TECHNICAL EDITOR

CompactPCI, a blend of VME and desktop-PC technology, holds promise as an industrial computer bus. A growing mass of products is making that promise a reality.

Introduced in 1995, CompactPCI (CPCI) promised the best of both the VME and PC worlds. CPCI offered a blend of VME's robust pin-and-socket connectors on Eurocard format with the PC's powerful and ubiquitous PCI bus. Its start-up was rougher than many vendors expected, however, and products were slow to emerge. Now, major VME vendors are adding CPCI to their board line-ups, and boards are becoming increasingly abundant as the CPCI community polishes its offerings.

The idea behind CPCI is sound. Use of the Eurocard format with pin-and-socket connectors provides a board system with proven reliability and a form factor familiar to industrial users. Use of the PCI-bus structure provides performance and economic advantages and imposes some of CPCI's limitations.

One major advantage CPCI has over other industrial buses is the performance of the underlying PCI bus. PCI offers a 32-bit-wide bus running at a clock rate of 33 MHz, yielding a transfer rate of 132 Mbytes/sec. The bus allows expansion to 64-bit bus width and a 66-MHz clock speed, bringing its maximum transfer rate to 528 Mbytes/sec. PCI's high transfer rates refer to block transfers. The PCI-bus structure is less suited to single-cycle transfers. PCI is somewhat inefficient when moving only a few bytes at a time across the bus.

PCI fan-out limits CPCI systems

Another limitation to the PCI bus is its fan-out capability. Conventional desktop PCI cannot handle more than eight to 10 loads on the bus. Even with only one PCI device on each board, the effect of connectors, which also count as a load, restricts PCI to three to four boards in a system. CPCI stretches this limit by imposing impedance and trace-length requirements on boards and connectors. This stretching yields a system of no more than eight boards, however, unless the CPCI backplane uses PCI-bus bridges to extend PCI's fan-out. With bridge chips, the bus capacity can equal that of other industrial buses.

Besides superior data-movement performance, use of the PCI bus brings CPCI a tremendous technology base from which to draw. Virtually every high-performance CPU available offers a PCI interface, making CPCI virtually platform independent. Further, CPCI designs can draw on the array of powerful yet low-cost I/O devices supporting the desktop-PC market. This ability to leverage PC technology gives CPCI an economic advantage over other bus structures, whose limited market size implies greater cost and fewer options.

Exploiting the PC market is a double-edged sword, however. The frantic rate of technology evolution in the PC market can make the availability of some devices uncertain. Parts appear and then become obsolete within a year. For the industrial embedded-computing market, with expected product lifetimes of 5 to 10 years, such rapid turnover is unacceptable. Fortunately, the PC technology that you can leverage includes more than individual devices. ASIC libraries, macrocells, and synthesizable designs for PC peripheral devices, as well as the expertise to design with them, also exist. Industrial vendors have the opportunity to take control of their design's product life while still exploiting PC technology.

Taken together, CPCI's pluses and minuses add up to a capable and economically attractive alternative to other industrial buses. Yet the bus has not seen the early success its developers envisioned. Several factors have contributed to this slow beginning. One was the chicken-and-egg scenario affecting many new technologies. Developers don't readily commit to a new technology without an assured source of supply. Typically, such assurance comes with a significant array of vendors and product options available to draw from. Yet vendors don't invest heavily in product development without a significant market.

That scenario appears to now be breaking down. An increasing array of CPCI vendors and products has come to market, with the number continually growing (Table 1). More companies have products under development. The available range of products should, in turn, attract more customers, further stimulating product development.

A second factor that held back CPCI's development was the difficulty that many vendors had creating CPCI boards. The degree of difficulty vendors experienced varied, but many report common factors. The problems were just an accumulation of small difficulties that made development sluggish. Developers designing their own CPCI boards may experience similar difficulties.

One of the most common problems vendors report was the difficulty transitioning from ISA-bus design rules to CPCI design rules. To achieve an eight-board fan-out with sufficient operating margin, CPCI signals require careful board fabrication. Controlled impedances, inline resistors, limited trace lengths, and eight- to 12-layer pc boards are part of CPCI's design needs but are unnecessary in desktop board designs. Vendors from the desktop-PC market, therefore, needed to adjust their design and fabrication practices.

Vendors also report that they had difficulties arising from the CPCI connector system. The specification uses pure-metric units for connector specifications but uses inches converted to metric units for board specifications. Some vendors found their CAD systems unable to handle the mixed units, resulting in an inability to put all components on grid.

Manufacturing, too, had trouble with the mixed units. Converting the pure-metric dimensions to nearest-inch equivalents resulted in unacceptable accumulated-tolerance errors. Vendors had to convert their mechanical design and fabrication to pure metric to meet CPCI's specifications. Connector assembly also proved to be a roadblock for some vendors. In addition to their hard-metric mounting pattern, connectors require press-fitting into the board. Some vendors found their assembly houses unable to handle the press-fitting operation.

The next obstacle in the early development of CPCI boards was board debugging. To test a new board's operation, CPCI systems needed to be working correctly. The PCI interface requires the operating system to initialize and configure a board during power-up. This requirement further implies that device drivers and other system-level software be operational when testing. In early systems, when all the boards and systems were new, the process became a Catch-22. The controller had to be working so that it could configure the system so that the designer could test the controller.

Leaping that hurdle provided vendors with stable test systems. The need for power-up configuration, however, continued to complicate the testing of peripheral boards and their drivers. If a developer discovered a problem during test, removing power from the board to repair the problem would change the system configuration. No guarantee existed that repowering the system would result in the same initialization of boards and registers. This inability to exactly re-create the failure condition slowed debugging efforts.

The power-up configuration slowed testing in other ways. Because the system had to reboot and return to the operational stages under test each time developers made a correction, developers spent a lot of time getting back to where they left off after each correction. Using an extender card and powering off only the board under test didn't help. The board, upon power-up, needed initialization commands that occurred only during system reboot. Vendors resorted to intelligent extender cards that would capture configuration information and reinitialize the board under test to bypass these power-up requirements.

Early CPCI developers, then, faced and overcame a series of minor setbacks to get their products to market. The lessons they learned during that effort improved their manufacturing infrastructure and formed the basis of a major revision to the CPCI specification. The PCI Industrial Computer Manufacturers Group (PICMG) ratified Revision 2.1 of the CPCI specification in August.

Revision 2.1 introduces several significant changes. For one thing, the group rewrote the specification's wording and structure. The new wording organizes into sections what were intermingled mechanical, operational, and electrical specifications in Revision 1. The new version also distinguishes among recommended, required, and optional design elements.

Perhaps the most significant additions to the specification are mechanical. Both the connectors and the insertion/extraction mechanics changed. In addition, Re-vision 2.1 defines the connector placement for 6U boards and includes a new connector. The Revision also adds signal lines in anticipation of bringing hot-swap capability to CPCI.

The connector revisions stem partly from cost considerations. Revision 1 called for a single 47-row connector, J1, to carry all the PCI-bus signals. Revision 2.1 breaks J1 into a 25-row J1 and a 22-row J2 connector. The new J1 connector carries the signals for 32-bit PCI, and J2 carries the signals to extend PCI to 64 bits. Thus, vendors developing 32-bit CPCI boards avoid the extra cost and assembly difficulty of the 47-row connector.

Revision 2.1 also defines the connectors on the 6U-size board. The J3 and J4 connectors mirror J1 and J2 on the 3U board. The J5 connector resides in the board's center, providing additional user-defined pins on the backplane. This additional connector imposes limits on the system's card cage, however. Without J5, the backplane for CPCI would fit into a card cage designed for VME systems. The J5 connector, however, interferes with a stiffening bar that many VME assemblies use to strengthen the backplane against insertion forces. As a result, CPCI cages must eliminate the bar and thicken the backplane pc board to compensate.

The insertion forces a 6U CPCI board generates stimulated other mechanical changes as well. A fully loaded 6U CPCI board produces an insertion resistance as great as 120 lbs. Revision 2.1 calls for longer and stronger insertion/extraction levers to handle this force.

Revision 2.1 adds signals to the CPCI bus in anticipation of hot-swap capability. One added signal set produces geographic addressing for boards. These signal lines on the backplane give each card slot a unique pattern, allowing the system to determine where each logical element resides. Such addressing will be important in developing high-availability systems. The addresses allow a user or central controller to identify failing boards by their location so that the system can bypass the failed board and signal for its replacement.

The revision also adds a card-insertion-recognition pin. This signal pin alerts the system to the insertion or removal of a card while the system is running. The system can then configure the card and bring its capabilities online or arrange to bypass the card as required. Although the new specification changes in anticipation of hot-swap capability, the revision alone is not the answer. Operating-system software must also change to allow configuration of a board that arrives following system power-up initialization. Such changes are occurring. The next release of Windows NT will include such ability.

Still other software and hardware requirements must be in place for CPCI to offer hot-swap capability, and the PICMG is defining those requirements. A hot-swap subcommittee has established the use of staged pins and other passive backplane techniques for providing live insertion and is defining software and operator procedures for removing cards from and inserting cards into a live system. The subcommittee is also defining various levels of live-insertion capability. A dynamically configured system will allow an operator to change boards without affecting system operation. A high-availability system will allow the CPU to automatically bypass failed boards.

Other specs in the works

The addition of a hot-swap specification is not the only refinement to CPCI in the works. Other efforts include defining a backplane sub-bus to carry H.100 telephony signals and mapping I/O signals to the backplane. Force Computer is heading an effort to define a mapping of VME64 signals to the CPCI backplane, allowing the rival buses to cooperate in a single system. Force is also helping define a mapping of PCI Mezzanine Card (PMC) signals to the backplane. GreenSpring is doing the same thing for IndustryPack I/O modules. When PICMG accepts these specifications, the mappings will provide standard ways of bringing I/O signals off the backplane to the user interface.

With the start-up difficulties resolved and a new specification to provide clear guidance, CPCI vendors are poised to offer users a high-performance, high-reliability industrial bus with enough industry support to make the bus viable for long-term projects. Thus, CPCI has come off the rocky road of its beginnings and is ready to pull into the fast lane of applications acceptance.

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