October 23, 1997

Some designs send mixed signals

Clive "Max" Maxfield, Intergraph Computer Systems

The phrase "mixed signal" typically refers to designs containing both analog and digital functions or components, but this idea is an oversimplification. In the real world, every electronic component behaves in an analog fashion, but you can connect these components to form functions amenable to digital approximations.

As the clocking frequency of a system increases, the interconnections of circuits containing only digital functions begin to exhibit increasingly significant analog effects. At some point, these effects become significant enough that you must consider them in the analog domain. As the clocking frequency further increases, the digital functions themselves begin to exhibit analog effects. At sufficiently high frequencies, which vary by system and technology, digital and analog components and functions become almost indistinguishable.

Thus, "mixed signal" should actually refer to designs that exhibit both analog and digital characteristics. This distinction is important, because many designers are entering the mixed-signal arena, even though they may consider their designs to be purely digital.

Beware of terms such as "clocking frequency"

Many people associate high-speed design with higher clocking frequencies, but the two are not directly related. What is important is the rate of change of signals; that is, the speed of their "edges" (Figure 1).

The three signals in the figure all have the same frequency, but they transition between Logic 0 and Logic 1 values at different speeds. As the edge speed increases, you move closer to having a perfect square wave. However, a square wave is composed of multiple sine waves at different harmonics, so the closer you approach a perfect square wave, the higher the frequencies of the sine waves required to form it. This fact is also true of individual edges; the faster the edge rate, the higher the frequencies of that edge's harmonic components.

So, "clocking frequency" is something of a misnomer. When you increase the frequency of the system clock, you must also increase the edge speed of your signals to squeeze the same amount of activity into each clock cycle. The high-frequency components of these sharper edges typically cause problems. Thus, if you're working with signals with fast edges, you may experience high-speed-design problems in products driven by relatively slow system clocks.

Analog simulation

Except for applications such as computers, most electronic designs in the 1960s and early 1970s contained substantial amounts of analog circuitry. One reason was that relatively few digital functions were available as ICs, and most of those were at the SSI, MSI, and LSI level. (By one convention, SSI devices have one to 12 gates, MSI devices have 13 to 99 gates, and LSI devices have 100 to 999 gates.) In addition, speed requirements demanded that designers implement portions of designs in analog. Clock frequencies of typical mid-1970s digital circuits were relatively low, so analog circuitry typically handled signal processing and conditioning.

Universities began investigating computer-based analog design aids during the late 1960s. The University of California--Berkeley presented one of the first analog simulators resulting from these investigations in the 1970s: the Simulation Program with Integrated Circuit Emphasis (Spice). Spice 1 became available around the beginning of the 1970s, and the more popular Spice 2 appeared around the middle of the 1970s. In the late 1980s, Berkeley developed Spice 3, which was primarily Spice 2 rewritten in C and restructured to make it easier to add models. Unfortunately, Spice 3 contained and still contains problems, including some serious algorithmic bugs.

To understand the problems of cosimulating analog and digital simulators, you must first understand how these simulators operate. An analog simulator represents a circuit as a matrix of differential equations, and, for a given stimulus, the simulator solves the matrix iteratively as it attempts to converge on a solution.

Consider the circuit in Figure 2. The analog simulator's objectives are to quickly and efficiently determine and return accurate results. As the delta-time used to solve a differential equation approaches zero, the result the equation returns approaches its optimal accuracy. But, solving the equation an infinite number of times for infinitesimal time steps means that the computer never arrives at a final result. Ideally, the computer would use large increments of time and, therefore, solve the equation relatively few times, but the possibility of error increases as a function of the size of the time increment. For the circuit in Figure 2, assume a step function applied to V_IN, which would cause the response in Figure 3. To represent a more complex circuit, you would need more differential equations, each of which may affect the others. The fact that the equations can affect each other is the reason that the simulator stores the equations in a matrix and solves them simultaneously.

You might wonder how the simulator knows how well it is doing if it does not know the analytical solution. You can visualize this problem by calculating the square root of 30, for example. Using one technique, you may start with 5 and square that to get 25. You would then iteratively modify your starting number until you achieve a result that satisfied you, as follows:

5×5=25;
5.20×5.20=27.04;
5.30×5.30=28.09;
5.40×5.40=29.16;
5.45×5.45=29.70;
5.47×5.47=29.92.

This process is conceptually similar to the iterative approach an analog simulator employs to solve its differential equations and converge on a solution. "Convergence" means that the simulator has sufficiently powerful algorithms and the circuit is described using sufficiently accurate equations to enable the simulator to achieve a numerical solution.

If, after a specified maximum number of iterations, the simulator cannot converge on an acceptable solution, then it shortens the time step and tries again. Similarly, if the simulator converges on a solution using relatively few iterations, then it employs a larger time step to calculate the next point in the sequence. All modern analog simulators use a form of this adaptive time-step algorithm to achieve the optimal trade-off between simulation accuracy and CPU efficiency. This trade-off affects the cosimulation of analog and digital simulators, because digital designs use a fixed time step, but analog time steps can change dynamically.

Designers can spend an inordinate amount of time fine-tuning the simulator and adjusting the tolerances, thereby tightening or loosening the convergence criteria. Tightening the tolerances generally improves accuracy but lengthens the time the simulator takes to evaluate the circuit. Additionally, tightening the tolerances may result in the simulator's never converging. Of more concern is the fact that changing the tolerances can significantly modify the output from the simulator. Another problem is that some of Spice's core primitives have discontinuities in their equations, which can cause difficulties when the simulators try to converge in these discontinuities.

In comparison, modern analog simulators typically have more sophisticated core equations than Spice. Additionally, some modern simulators employ heuristic techniques that allow them to select different algorithms and attempt different solutions.

Traditionally, creating stimuli in the form of tables of numerical values could be almost as taxing as designing the circuit itself. Today's graphical environments can facilitate the construction of highly complex waveforms, allowing designers to graphically create waveforms using straight-line and freeform drawing. You can then modify such waveforms using spline-based techniques, or you can mathematically manipulate the waveforms by multiplying one by another. In addition to displaying waveforms in the time domain, designers can also display and modify the waveform's spectral components, magnitude, and phase. These techniques allow designers to construct complex real-world waveforms, which include such features as nonlinearities, overshoot, ringing, and high-frequency noise.

Analog simulators need not operate solely at the transistor level; they may support multiple levels of modeling abstraction, including digital logic primitives, such as gates and registers, with analog-interface characteristics. Also of interest are analog behavioral languages, which let you represent portions of a design at a high level of abstraction. Some analog simulators work primarily in system-level and control-engineering design tasks and are relatively poor at the transistor level that IC design requires.

Like their analog counterparts, digital simulators also started out as university projects. Digital simulators are based on the concepts of a fixed time step and an "event wheel," which schedules events to occur in the future. (A digital simulator does not blindly simulate every time step. Once a simulator executes all the actions of a time step, it skips any empty time steps and leaps directly to the next time step in the event wheel that has an action to perform.) When an input to a digital function changes state, the simulator evaluates the logical function to determine whether this change should cause a corresponding change at the output. If the simulator determines that an output change is required, it looks up the delay associated with this change and then posts an event to the event wheel for action at the appropriate time.

The original digital simulators targeted gate-level TTL designs. Additionally, the original simulators were based on proprietary HDLs, which were generally little more than netlists calling simulator primitives. Early digital simulators were based on a distributed delay model, in which each primitive gate had its own delays. This model remains useful for some applications, but modern digital simulators typically also support pin-to-pin delays, which are advantageous for modeling the cells in IC designs. Additionally, because early digital simulators represented TTL at the board level, they predominantly used an inertial-delay model, which rejected pulses that were narrower than the gate's propagation delay. The inertial-delay model is insufficient for components such as delay lines, so designers augmented digital simulators to support transport delay specifications, in which pulses, regardless of their width or the propagation delay of the logic gate, always propagate (Reference 1).

Mixed-signal verification strategies

The traditional approach for designs containing both analog and digital elements is to partition the design at the beginning of its development cycle. The digital and analog portions are then captured and verified in isolation, and they are reunited only at the prototyping stage. This simple technique may be appropriate for highly partitioned designs without feedback. However, this strategy does not provide the designer with much confidence that the digital and analog portions will interface correctly. A development of this technique is to verify one portion of the design, analog or digital, using the relevant simulator. In this approach, the simulator captures and stores the output, which is subsequently coerced, or mapped, into a suitable format for use as stimulus for the other portion. Again, this technique may be suitable for highly partitioned designs without feedback, but it is typically painful and time-consuming.

You cannot categorize either of these techniques as true mixed-signal verification. To be mixed-signal, the simulation environment must support the concurrent verification of both the analog and the digital portions of the design. There are many cases, however, in which true mixed-signal verification is the only realistic alternative. Designs in this category include those exhibiting tightly coupled feedback between the analog and digital portions. Such designs, for example, would be circuits employing PLL techniques. Additionally, the advent of multimedia technology is dramatically increasing the use of DSP techniques, which can involve sophisticated and tightly integrated combinations of analog and digital circuitry.

High-speed designs employing only digital components may also require mixed-signal verification. Although you can verify most of a design using a digital simulator, it may be necessary to subject the critical interconnection paths to a more exhaustive analog analysis. In some cases, it may be sufficient to perform signal-integrity analysis offline on the interconnect only, but cases in which the parasitic effects depend on the state of other signals may mandate a mixed-signal approach.

A/d, A/D, and a/D

Until recently, the phrase "mixed-signal simulation" has typically been associated with the cosimulation of analog and digital simulators, but a more precise classification of simulation technology has begun to emerge. In that classification, "D" stands for pure digital simulation; "a/D," for digital simulation with native analog capability; "A/D," for cosimulation of analog and digital simulators; "A/d," for analog simulation with native digital capability; and "A," for pure analog simulation.

Designs containing large, complex portions of analog and digital may mandate the use of an A/D technique, which involves linking analog and digital simulators. Many designs, however, may respond to a/D or A/d evaluation. You typically use the a/D technique for primarily digital designs containing some analog. However, in this case, the analog portions are usually relatively large functions, which are amenable to behavioral representations; for example, A/D converters. Also, the a/D technique relies on a digital simulator that can support C models or VHDL models with signals of type REAL.

By comparison, the A/d technique relies on the use of an analog simulator that inherently understands the concept of digital primitives, such as logic gates and registers. The simulator handles these gates digitally, but the gates can have associated analog-interface characteristics, such as input and output impedances, input switching thresholds, output slope, overshoot, and frequency damping. A modern analog simulator with A/d capability can simulate a few tens of thousands of logic gates in this manner. The A/d technique is typically of use with primarily analog designs containing some digital functionality in the form of relatively simple logic functions.

The A/d technique is interesting primarily because analog simulators with this capability usually contain their own versions of event wheels. This property can be significant when you want to cosimulate the analog simulator with a digital simulator.

Alternative cosimulation strategies

Before considering A/D cosimulation strategies, you should consider the environment necessary to support full mixed-signal simulation. Today's mixed-level design practices require that you represent each portion of a design at the most appropriate level of abstraction. On the digital side, the design system should ideally allow you to represent portions of a design using graphical techniques, such as state diagrams, state tables, and truth tables; as textural HDL; as gate-level schematics or netlists; and as physical devices interfaced using a hardware modeler. Similarly, on the analog side, the design system should ideally allow you to represent portions of a design using an analog behavioral language, as native digital logic with analog interface characteristics, and as transistor-level schematics or netlists.

Such a system requires that some hierarchical blocks contain analog views and that some contain digital views. Additionally, the analog and digital portions of a design may not always be amenable to being partitioned into discrete blocks. Thus, the system should also support analog and digital elements in the same block; for example, primitive logic gates along with transistors, resistors, and capacitors.

After you capture the design, the system should be capable of automatically partitioning the analog and digital functions and presenting them to the appropriate simulation engines. Additionally, the system should inject special elements to interface the analog and digital functions (Figure 4). For example, when a digital signal enters the analog world, the interface element must map the "sharp" digital edges into analog equivalents, such as impedances and slopes. To avoid manual intervention, the system should automatically inject the appropriate interface element based on a technology parameter associated with the digital symbol. The system should also support user-defined technologies for full-custom applications, cross-probing of analog and digital signals from the schematic, and the ability to display both analog and digital traces in one analysis window.

A number of cosimulation strategies are available for design verification, including unified, simulation backplane, glued, and coupled. In the unified approach, the digital and analog simulation engines share a simulation database. This approach offers the fastest simulation, but the engines themselves are typically inferior to those of the other approaches. "Inferior" in this context implies only that the engines offer limited support of modeling abstraction and perform few types of analysis. For example, unified solutions, even when performing "pure" analog simulations, typically can perform only time-domain analysis.

Vendors of simulation backplanes usually promote the devices' plug-and-play capability; that is, the devices let you combine digital and analog simulators. However, they usually support few simulators, the final solution provides only the smallest subset of capabilities all the simulators offer, and they can entail significant initialization problems. Also, having three processes communicating with each other--the two simulators and the backplane--incurs a significant overhead.

In the glued approach, two simulators are linked via a C interface in a master/slave relationship. The digital simulator is typically the master, which "sees" the analog simulator as a C model. The glued approach offers tighter coupling and better accuracy and efficiency than a simulation backplane.

The coupled approach resembles the glued technique in that they both involve linking the two simulators via a C interface. However, the coupled approach is based on an analog simulator with A/d capability, in which the analog simulator inherently understands the concept of digital primitives, such as logic gates and registers. Because analog simulators with this capability usually contain their own versions of event wheels, both simulators can mutually schedule and access events on the wheel. The proponents of this scheme believe that it offers the best features of the unified and the glued techniques.

A major consideration of the alternative cosimulation strategies is the way in which the analog and digital simulators are synchronized in time. The two most common synchronization techniques are the Lockstep and Calaveras algorithms. The Lockstep algorithm requires that the two engines are locked together in time throughout the simulation, which means that the digital engine must take the smallest time step that the analog engine does. Additionally, the first engine to complete a time step must wait for the other engine to catch up. By comparison, the Calaveras algorithm allows one simulator to run ahead of the other. If the simulators subsequently determine that evaluations in one domain would have affected the other domain, then the algorithm "winds back" time as far as is necessary to account for the interaction, and the process is repeated with the new data.

Champions of the Calaveras algorithm would say that the Lockstep technique is inefficient, because one simulator is always waiting for the other. Similarly, proponents of the Lockstep algorithm would say that the Calaveras technique is inefficient because the simulators are constantly throwing data away, and the algorithm may simulate a group of time steps several times. In reality, the performance of each approach depends strongly on the topology and content of the circuit under evaluation. One technique that might improve the Calaveras algorithm would be to monitor simulation activity to see which simulator most frequently runs ahead and to then vary the proportion of CPU time that is available to each simulator to balance the load.

Mixing A/D and A/d

A/d models combine the simulation accuracy of pure analog with simulation speeds as much as 250 times faster than their transistor-level equivalents. However, this technique is still substantially slower than simulating logic gates using a digital simulator. More important, the A/d technique is limited in the number of logic gates it can simulate, but ICs can contain many hundreds of thousands of logic gates. You can solve this problem by combining A/D and A/d simulation techniques (Figure 5). Devices at the ULSI stage typically contain complex digital macro functions, such as µP cores, memory blocks, and communications functions. You can individually characterize these functions and then represent them as C models; as behavioral HDL models, such as VHDL or Verilog HDL; as physical devices interfaced using a hardware modeler; as gate-level netlists; or as a combination of these techniques.

Thus, you can simulate the strongly characterized digital macro functions in the digital domain, which you can interface to the analog domain using A/D mixed-signal techniques. Meanwhile, you can simulate the critical paths in the remaining glue logic--the simple digital primitives linking the macro functions--in the analog domain using A/d mixed-signal simulation techniques.

Reference

1. Maxfield, Clive "Max," "Digital logic simulation: event-driven, cycle-based, and home-brewed," EDN, July 4, 1996, pg 129.

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