October 23, 1997

RS-232C handshake lines transfer data frames

SK Shenoy, Naval Physical & Oceanographic Lab, Kochi, India

The asynchronous RS-232C interface is a simple, low-cost option for interconnecting processor-based systems, but this character-oriented interface supports no direct mechanism to transfer variable-sized messages as self-contained data packets. However, you can use the DTE-DCE handshake lines, namely DTR and DSR, to implement packet-level data exchange. The proposed method interconnects the DTR and DSR of the two systems and uses these lines to indicate packet boundaries.

This method wastes no CPU overhead to determine packet boundaries. Instead, the UART interrupts the CPU at the start and end of a packet. This method is data-transparent and supports binary-data exchange. The packet-boundary detection is immune to data corruption and loss. You can also make the method more robust by including data-length and check-sum fields in the frame to enable error detection.

The transmitting station begins a packet transmission when it activates DTR by forcing it low (Figure 1). On the receiving end, any change in DSR's state interrupts the UART. When this interrupt happens, the receiving side's ISR finds the DSR active, which indicates the start of the packet. While DSR is active, the ISR stores all subsequent received bytes in the receive buffer with receive_count as an index. The transmitter deactivates the DTR at the end of the packet, which raises another interrupt at the receiver. Because the DSR is now inactive, the ISR recognizes the end of packet and calls the packet-processing function. The data bytes forming the message are thus sent while the transmitter's DTR is active.

You can also add flow control using the CTS/RTS lines to this transfer scheme to avoid receive overrun conditions, especially if the receiving station is running real-time software with the receive interrupt at a lower priority. The CTS and RTS of the two stations interconnect. The receiver activates RTS in response to a start-of-frame interrupt and deactivates RTS after a byte is received and until the receiver is ready for the next transmission. The transmitter transmits only if the CTS is active (low) (Figure 2).

A Turbo C program demonstrates the transfer of variable-sized messages between two PCs with 8250-compatible UARTs using this technique and with the PC COM ports connected with a null modem cable. The same procedure works with most other UARTs. Click here to download the file from DI-SIG, #2100.

Setting bit 0 of the modem-control register makes DTR active (low), and vice versa. Similarly, bit 1 controls RTS. You obtain the status of the DSR/CTS input from the modem-status register. Note that the register holds the complement of the actual state. Any change in state of the DSR line sets bit 1 of this register. Bit 5 reflects the complement of the DSR line, and bit 4 reflects the complement of the CTS. To enable interrupts when the state of DSR changes, the UART initialization must set bit 3 (modem-interrupt enable) of the interrupt-enable register. Setting bit 0 enables receive interrupts. The ISR checks bits 1 and 2 of the interrupt-identification register to identify the interrupt type. (DI #2100)

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