October 23, 1997

WHAT'S HOT IN THE DESIGN COMMUNITY

22V10: still going strong

With all the industry focus these days on 100,000-gate CPLDs and FPGAs, HDL synthesis, and core-based design, it's easy to forget the humble PAL. However, plenty of these parts still find use as fast state machines and address decoders, as a means of implementing last-minute board-design changes, and as integrators of miscellaneous discrete logic. The highly flexible 22V10 is perhaps the most popular PAL, with plenty of low-cost or even free tool support; Lattice Semiconductor and Philips Semiconductors are among the companies still investing in it.

Lattice has migrated its GAL22V10 to a 0.45-µm-lithography EEPROM process, obtaining a 20% speed boost. This 5V part, in a PLCC package, features a 4-nsec input-to-output propagation delay and 3.5-nsec clock-to-output register timings. Better yet, Lattice prices the part on a parity with the previous 5-nsec device. Also, the company's in-system-programmable; 7.5-, 10-, and 15-nsec; 0.75-µm-based ispGAL22V10 parts now cost the same as their non-ISP counterparts.

Philips, continuing its low-power focus, has also announced EEPROM-based 22V10s based on the company's CoolRunner full-CMOS architecture. The 3V version specifies a 10-nsec propagation delay, less than 45 µA of static power, and less than 15 mA of dynamic power at 50 MHz. Its 5V counterpart offers a 7.5-nsec propagation delay. Packaging options include TSSOP, SOJ, and PLCC.

The 4-nsec Lattice GAL22V10 costs $8.75 (1000) and is now in production. Both the 7.5-nsec, 5V and the 10-nsec, 3.3V versions of Philips' 22V10 in SOJ and PLCC packages cost $4.40 (10,000), and both are now in production.

--by Brian Dipert

Lattice Semiconductor, Hillsboro, OR. 1-503-681-0188, fax 1-503-681-3037, www.lattice.com.

Philips Semiconductors, Albuquerque, NM. 1-505-822-7629,
fax 1-505-822-7804, www.philips.com

RISC architecture is small yet mighty

With Mighty Mouse as its official mascot, Motorola is launching MCore, a 32-bit RISC architecture. MCore uses a four-stage pipeline to execute two-thirds of its 95 basic instructions in one clock. Similar to Hitachi's SuperH 32-bit architecture, MCore uses 16-bit, fixed-length instructions and a register file with 16 general-purpose registers and an alternative register file for context switches. Unlike SuperH, which shadows only eight of its general-purpose registers, MCore shadows all 16. MCore implements only 86% of its operation-code space, allowing some instruction head room for future generations.

The architecture supports 8-, 16-, and 32-bit data types, although misaligned-data accesses force a misaligned-data exception. You can mask the misaligned-data exception using a control bit in the process-status register. Although you can't access MCore's registers as bytes and words, instructions can sign-extend non-32-bit data types. A barrel shifter shifts as many as 32 bits in one cycle. The architecture also contains a find-first-one unit and result-feed-forward hardware. The feed-forward hardware allows a subsequent operation to use a result while the CPU writes the result back into the register file. The first version of the MCore architecture offers limited support for hardware multiply and divide; it uses a 2-bit per clock, overlapped-scan, modified Booth algorithm with early-out capability to reduce execution time for operations with small multipliers.

MCore contains a 32-channel interrupt controller. The processor can take in an asynchronous interrupt and get to the first instruction of an interrupt-service routine in six clocks. The CPU determines interrupt prioritization through software, and you can use the find-first-one value as an offset into a jump table. An interrupt-control bit in the program-status register allows an event to interrupt multicycle instructions, such as the load/store multiple-register instructions. For less real-time-critical applications, you can set this bit to prevent the interrupts from breaking into instructions.

MCore's hardware-accelerator interface supports various hardware-specific functions. You can use one of several interface mechanisms. For example, a register-snooping mechanism reflects updates of MCore's registers across the interface without explicit passing of parameters from the core to the hardware accelerator.

Besides a 16-bit external interface to minimize power consumption, MCore also implements three software-controlled low-power modes and controls functional-unit clocking. The core runs as low as 1V, although the first products operate from 1.8 to 3.3V.

Motorola targets the first MCore device as a cellular baseband processor. In addition to an MCore core, 2 kbytes of SRAM, and 16 kbytes of ROM, the device contains a Motorola 56600 DSP, a smart-card interface, a keypad interface, a TDMA timer, and other digital communications features. The next device will be available for sampling in the first quarter of 1998. It is a standard part containing 32 kbytes of SRAM, 128 kbytes of ROM, a real-time clock, a watchdog timer, a programmable interval timer, a keypad interface, six PWMs, GPIOs, two UARTs, and an interval serial peripheral interface that allows the device to read system peripherals periodically. This device comes in a 100-pin TQFP and operates from ­40 to +85ºC from a 1.8 to 3.6V supply. Driven by a 1× clock, this device operates as fast as 50 MHz and consumes 0.41 mW/MHz at 1.8V.

To support the development tools for MCore, Motorola has established a validation center to ensure that third-party vendors comply with the Motorola-defined Application Binary Interface (ABI). ABI ensures that MCore tools will work together in a development environment. Although MCore has limited tool support, the tools that are available should handle most of your development needs. Diab Data (Foster City, CA, www.ddi.com) supplies a C/C++ compiler, and Motorola offers a Gnu tool kit. Software Development Systems (Oak Brook, IL, www.sdsi.com) supplies a simulation and debugging tool that offers memory and peripheral simulation. Integrated Systems Inc (Sunnyvale, CA, www.isi.com) and Microtec (San Jose, CA, www.mri.com) have ported their pSOS+ and OS-9000 RTOSs, respectively, to the MCore architecture. Hewlett-Packard (Palo Alto, CA, www.hp.com) offers a hardware-based runtime controller that operates through the on-chip emulation circuitry and MCore's JTAG interface. Motorola also offers an MCore evaluation board.

--by Markus Levy

Motorola, Austin, TX. 1-800-765-7795, ext 605, www.motorola.com/mcore.

Wescon/IC Expo comes to Silicon Valley

Wescon, North America's largest electronics trade exhibition and conference, takes place in San Jose, CA, and Santa Clara, CA, on Nov 4 through 6. The Wescon/IC Expo event combines more than 1300 exhibits with a technical program covering a range of technical subjects. You'll also hear keynote talks by John Morgridge, chairman of Cisco Systems; Chet Silvestri, president of Sun Microsystems; and Curtis Crawford, president of Lucent Technologies' Microelectronics Group.

The show's technical program comprises dozens of short courses, application-engineering workshops, plenary sessions, and technical sessions. You can choose from communications, IC technologies/power management, multimedia, software, and design/test/manufacturing technology tracks.

Many events are free or have just a nominal cost. Wescon is also handling transportation between show venues by supplying free light-rail transportation between the San Jose and Santa Clara convention centers.

--by Jim Lipman

Wescon/IC Expo '97, Los Angeles, CA. 1-800-877-2668, ext 244,
fax 1-310-215-3976, www.wescon.com.

Micromachined pressure
sensors fuel drop to lower ranges

Although temperature is the most frequently measured physical variable--and with good reason--many applications need to or should measure pressure or acceleration. Two bulk micromachined sensors from the Silicon Microstructures Division of Exar Corp provide high-level analog outputs proportional to these parameters and for relatively low full-scale ranges.

The SM7140 capacitive accelerometer is available in 2 to 300g ranges, all with 80-dB SNR. Resolution for these units, which can withstand 2000g shocks, is approximately one part in 1000; thus, the 2g unit can resolve forces as low as 0.0002g. (Don't tap the table!) The temperature-compensated accelerometers operate from an 8 to 20V supply, producing a 2.5V output at 0g with a ±2V swing over their full range. Each device comes in a plastic enclosure measuring approximately 1×0.8×0.3 in. with an integrated shielded cable and connector. The devices cost $100 (10,000).

You can use the SM5752 pressure sensor for ranges as low as 0 to 0.15 psi full scale, although ranges as high as 3 psi are available. The similar SM7512 family covers full-scale ranges from 0 to 5 psi through 0 to 100 psi. All devices in the families are internally calibrated and compensated for zero, span, and temperature coefficient. The internal signal-conditioning circuitry produces a full-scale output range of 0.5 to 4.5V and operates ratiometrically from a 5 to 15V supply. The SM5752 has 0.3% full-scale linearity, and overpressure capability is three times full scale. These pressure sensors come in eight-pin DIP packages and cost $12.50 to $15 (1000), depending on model.

--by Bill Schweber

Exar Corp, Fremont, CA. 1-510-668-7000, fax 1-510-668-7017, www.exar.com.

BIST tool digs into embedded memories

Viewlogic joins the ranks of companies offering built-in self-test (BIST) products for embedded memories. You use Sunrise MemBIST, like earlier products from Mentor Graphics (Wilsonville, OR) and LogicVision (San Jose, CA), to add testability features to on-chip memory blocks. With BIST, you need no memory test-vector development or added area burden of embedded-memory access to check out your memory design.

MemBIST, part of the Sunrise TestGen tool suite, supports SRAM, ROM, and DRAM modules and allows you to test these memories at full system speeds. The tool handles single- and dual-port, synchronous or asynchronous memories. MemBIST lets you choose from 12 built-in memory test algorithms. You can also define custom test algorithms to use on specialized memory configurations. Going beyond test of the embedded memory core, MemBIST also creates test features in the memory BIST logic for automatic test-pattern generation (ATPG) of the memory's I/O-interface logic.

Viewlogic based MemBIST on graphically entered memory characteristics; it generates Verilog RTL code for all the BIST modules for the chip's embedded memory blocks. In addition, it includes an RTL testbench and behavioral models of the memory blocks to use with a logic simulator to verify your memory design. The software also gives you a model of the BIST controller that all memory blocks on the chip share. MemBIST generates a synthesis script for use with the RTL BIST logic to synthesize netlist-level BIST logic.

The price of the basic MemBIST package for generating SRAM and ROM BIST-design elements and testbenches starts at $40,000. You can get options for DRAM BIST and design diagnostics at additional cost.

--by Jim Lipman

Viewlogic, Marlborough, MA. 1-508-480-0881, fax 1-508-480-0882, www.viewlogic.com.

Planar transformers drop
into high-speed switchers

Planar transformers from Signal Transformer Co provide a typical efficiency of 97% in high-frequency switching power supplies. Their planar design replaces traditional copper wire with a pc-board winding and a stamped copper sheet. The design uses a low-profile ferrite core that results in a low-profile package. A 200W transformer, for example, measures only 0.55 in. high and is lighter than equivalent-rated, conventional, high-frequency transformers. Typical switching frequency is 360 to 400 kHz. The transformers are available in power ratings from 45 to 2800W, with prices of $5.50 to $27.80 (OEM), respectively.

--by Bill Travis

Signal Transformer Co, Inwood, NY. 1-516-239-5777, fax 1-516-239-7208.

Smart-battery power monitor
estimates "time remaining"

It's often not enough to know the approximate amount of charge left in a battery: You also need to know how much corresponding talk or standby time that cellular phone has left. A circuit based on the bq2018 power monitor from Benchmarq Microelectronics gives you some of the information you need to make that calculation. Designed to nestle in smart battery packs, this eight-pin, 150-mil SOIC is a charge and discharge counter that provides the required "gas-gauge" resolution, because it can resolve signals as low as 12.5 µV. An internal offset calibration improves accuracy.

The device also has 128 bytes of nonvolatile RAM, of which 115 bytes are user-programmable for storing information such as battery ID or charge data. The RAM consumes only 100 nA of current, so it can retain data for more than a year using a modest 1200-mAhr battery drained to one-tenth of 1% of its nominal capacity. An internal temperature sensor features 2ºC accuracy, in 10ºC steps, commensurate with the application requirements. The bq2018 also includes a timer, which eliminates the need for external components and enhances system accuracy by canceling out most timebase errors. You connect the device to the system microcontroller's UART or single-bit port; communication occurs at 5 kbps with a command/response protocol. The IC costs $1.85 (10,000).

--by Bill Schweber

Benchmarq Microelectronics Inc, Dallas, TX. 1-972-437-0581,
fax 1-972-437-9195, www.benchmarq.com.

pi attenuator targets PCS/cellular systems

Model PI-820 broadband PIN-diode attenuator from KDI/Triangle Electronics suits analog applications in the 100-MHz to 2-GHz range. It uses a surface-mount ceramic package especially suitable for personal-communications systems. The pi-network device provides 0- to 40-dB attenuation with a control voltage of 0 to 10V, with 3.5-dB typical insertion loss. Specifications for the PI-820 cover the 800-MHz to 2-GHz range; you can optimize the attenuator for lower frequency ranges by simply changing capacitor values.

The attenuator uses a four-diode network in a symmetrical pi configuration. The use of two diodes opposed in the series path increases the maximum attenuation and doubles the upper frequency limit for a given attenuation over three-diode structures. In addition, the 180º phase relationship of the diode placement results in the cancellation of even-order harmonic products. The device costs $11.75 (1000).

--by Bill Travis

KDI/Triangle Electronics Inc, Whippany, NJ. 1-201-887-8100, ext 500,
fax 1-201-884-0445.

Not just an ASIC prototype

Gatefield Corp (formerly, Zycad) has refocused after spinning off its logic-verification division. The company has introduced its first FPGAs with embedded RAM, the GF260F ProASIC family. Gatefield developed the family--one of the finest grained programmable-logic-cell families in the industry--as the silicon "engine" of the company's ASIC hardware simulators. Gatefield also touts the ProASIC's flash-memory-configuration element, which the company claims takes up less silicon area than SRAM and EE-PROM alternatives on equivalent process lithographies.

Gatefield built all the GF260F family devices on a 0.6-µm process. The members are the GF260F100 with 43,000 maximum logic gates plus 14 kbits of SRAM, the GF260F180 with 92,000 maximum logic gates plus 23 kbits of SRAM, and the GF260F310 with 123,000 maximum logic gates plus 46 kbits of SRAM. The SRAM comprises groupings of 256×9-bit memory blocks. The memory-block flexibility includes dual- or single-port SRAM and FIFO configurations and various width and depth options to maximize performance and avoid the need to use logic resources. For designs that need no embedded RAM, Gatefield offers the 0.8-µm GF100K, 0.7-µm GF200F, and 0.6-µm GF250F families.

The GF260F180 is now available for sampling, comes in a super BGA package, and costs $599 (100). The GF260F100 and GF260F310 will follow in the first and second quarters, respectively, of next year. The company also plans to offer ceramic PGA and metric-quad packaging options. EDA support includes the ASICmaster back-end tool suite and Memorymaster embedded memory compiler. Software runs under Hewlett-Packard and Sun Unix and Windows NT.

--by Brian Dipert

Gatefield Corp, Fremont, CA. 1-510-623-4400, fax 1-510-226-0147, www.gatefield.com.

New tool speeds design
of high-speed pc boards

The SpecctraQuest interconnect design tool from Cadence combines a board-router and a timing-driven bus designer. The tool adds several features to help you design high-speed pc-board buses. SpecctraQuest provides component-level buffer-delay compensation, I/O-cell macromodeling, and Spice-subcircuit modeling of connectors and packages. You can include third-party Spice connector models in bus simulations, along with packaging parameters, such as wire-bond and package-lead-frame parasitics.

You use a timing-driven bus designer within the pc-board design flow to dynamically explore bus operation and determine onboard bus timing over multiple clocks and with multiple signals. SpecctraQuest lets you see the effects of interconnections on bus performance during board floorplanning. The tool also includes the SigWave viewer for checking simulation waveforms. You can save your bus models along with their input stimuli for sharing within design teams and for other designs.

You can get SpecctraQuest now; the timing-driven bus-designer component of the tool is still in beta test and will be in production in the first quarter of next year. You have your choice of Unix or Windows versions of the tool. Prices start at $19,000 for the basic tool. If you include signal-integrity and timing options, the price is approximately $50,000. With EMC and thermal-design options, the tool costs around $25,000 and $30,000, respectively.

--by Jim Lipman

Cadence Design Systems, San Jose, CA. 1-408-943-1234,
fax 1-408-943-0513, www.cadence.com.

Chip set delivers ultraportable GPS

A new highly integrated chip set from GPS (Global Positioning System) pioneer SiRF Technology reduces power requirements and allows designers to add GPS capabilities to ultraportable devices, such as cell phones. The new SiRFstar1/LX chip set comprises the GRF1/LX RF front end, the GSP1/LX GPS signal processor, and companion GPS software. The new chip combines power-management and low-power-IC design techniques and requires only 1/15 the power of SiRF's earlier chip set (For more information on SiRF and other GPS-IC vendors, see "Time, position, and velocity? Just ask your GPS chip set," EDN, March 3, 1997, pg 50).

The chip designers cut power consumption by two-thirds by moving to 3.3V, 0.35-µm IC technology. Running at full power, the new two-chip set requires 360 mW. SiRF also parlayed its considerable advantage in fast reacquisition of a GPS signal to develop the TricklePower power-management mode. The SiRF1/LX chip set can reacquire a GPS signal in 100 msec, whereas many GPS chips require 1 sec. GPS receivers, meanwhile, typically update position only once per sec. TricklePower allows the chip set to maintain the 1-sec update rate, yet the chip set enters a sleep mode for almost 90% of each 1-sec cycle. This technique results in an average power demand of 75 mW for the GPS circuitry.

SiRF is shipping samples of the 1/LX chip set now and plans production for the first quarter of next year. The chip set will sell for $29.95 (10,000), and an evaluation kit costs $995.

--by Maury Wright

SiRF Technology Inc, Santa Clara, CA. 1-408-980-4700, www.sirf.com.

Top-port audio transducers
are sound idea for telecomm

The MNT surface-mount audio transducer from Star Micronics uses a top-port structure that's ideal for cellular phones, pagers/beepers, and cordless telephones. The transducer measures 9×9×4.5 mm (half the size of typical audio transducers) and weighs only 1g. Operating voltage is 1 to 4V, for a sound output of 85 dB minimum and 90 dB typical at 10 cm and 2670 Hz. The transducers come in a tape-and-reel format for pick-and-place production machinery. The MNT costs $3.07 (1000).

--by Bill Travis

Star Micronics America Inc, Piscataway, NJ. 1-908-572-9512, ext 548,
fax 1-908-572-5095.

Resistor networks squeeze
termination pitch to 0.025 in.

Series 753 resistor networks from CTS offer a termination pitch of a mere 0.025 in. The networks afford packaging density that's more than double that of 0603-sized chips, and more than six times that of 0805-sized chips. A 24-pad device with 22 bus resistors measures only 0.08 in. wide and provides a density of as many as 800 resistors/sq in. An added advantage of the device's size is reduced parasitic capacitance and inductance components. The networks can thus operate at frequencies exceeding 1 GHz. The networks are available in standard 12- and 24-pad configurations. A 24-pad network costs less than $0.80 in production quantities.

--by Bill Travis

CTS Corp, Berne, IN. 1-219-589-3111, fax 1-219-589-3243, www.ctscorp.com.

Serial-interface IC eases
meeting multiple standards

Flexibility and compliance challenges abound when you have to certify your router, Internet-access-device, or similar networking-equipment-system designs to meet multiple interface standards. Exar's XR-T4000 eases the task by supporting multiple protocols in one software-configurable IC. The 100-pin TQFP device complies with V.35, V.36, EIA-530 (A), RS-232C (V.28), X.21, and RS-449 standards, with eight receivers and eight transmitters for data-terminal- and data-communications-equipment operation. The IC provides high-voltage protection, eliminating the need for external discrete components.

The interface IC also provides a variety of loop-back modes to simplify diagnostics and minimize the need for external circuitry, along with an internal oscillator to generate the needed clock signal for stand-alone diagnostics. Users can disable internal filters, which protect the control signals--RI, RL, DCD, DTR, and DSR--against glitches. The XR-T4000 requires 5, 12, and ­6V supplies and costs $16.26 (25,000). Exar is also releasing the XR-T7245 T3 and XR-7234 E3 user-network-interface ICs for ATM applications, which comply with Utopia Level 2 specifications.

--by Bill Schweber

Exar Corp, Fremont, CA. 1-510-668-7000, fax 1-510-668-7017, www.exar.com.

Windows CE single-board computer debuts

Eclipse International's ES2110, the first single-board computer for embedded Windows CE applications, targets instrumentation, factory automation, process controls, data-collection terminals, point-of-sale devices, and other embedded applications. Eclipse based the device on Hitachi's (Brisbane, CA) 72-MHz, 32-bit SH-7709 RISC µP, and the company preloaded Windows CE into flash memory. The ES2110 requires a 3.3V power supply and has a 3×4-in. (75×100-mm) footprint for low-power, compact application needs.

Eclipse wrote and optimized common peripheral-device drivers and precompiled the OEM abstraction layer with the operating-system kernel, thus cutting software-development time and effort. Because Microsoft (Redmond, WA) built Windows CE on a well-established application-programming interface and development environment, the ES2110 can speed time to market for developers of embedded systems.

The device also includes a graphics controller supporting QVGA, VGA, 1/2VGA, black-and-white, 8-bit color-depth, and touchscreen LCDs. The ES2110 also provides infrared communications using IrDA 1.0 at 115 kbps, two PC Card Type II sockets, PS/2 keyboard support, three serial ports, and one parallel port. The ES2110 costs less than $500 (OEM). Eclipse also offers the PathFinder evaluation system comprising the ES2110 and a second board that includes the power supply and connections for testing numerous I/O functions. The kit costs $4995 with a thin-film-transistor VGA LCD, a keyboard, and software.

--by Kasey Clark

Eclipse International Inc, Mountain View, CA. 1-650-691-6400,
fax 1-650-428-0292, www.eclipseint.com.

Power-factor-correction
ICs trim harmonic distortion

Targeting electronic ballast and offline switching-power-supply applications, the KA7525 and KA7526 power-factor-correction ICs from Samsung Semiconductor help your offline application meet European IEC standard NC61000-3-2 for minimizing ac-line corruption. Each device includes an internal start-up timer for stand-alone applications, an overvoltage comparator to eliminate runaway output voltages that can occur when the load is suddenly removed, cycle-by-cycle current limiting, a clamp that limits peak current in the switch, and a totem-pole output for driving a power MOSFET. Maximum supply voltage is 30V dc, with ±500-mA peak drive current and 5-mA typical operating current.

The devices are similar, except that the KA7525 uses an internal high-gain amplifier, whereas the KA7526 em-ploys a high-performance transconductance amplifier. The KA7525 IC features a 10V start threshold voltage and 2.1V undervoltage lockout hysteresis; the corresponding figures for the KA7526 device are 13 and 5V. Both ICs are available in eight-pin DIPs and SOPs and cost $0.80 (10,000).

--by Bill Schweber

Samsung Semiconductor, San Jose, CA. 1-408-954-7000,
fax 1-408-954-7286, www.sec.samsung.com.

Gigabit Ethernet transceivers meet high-bandwidth requirements

Two new transceivers from AMD and Vitesse are filling the need for high-bandwidth transmission of complex data over Gigabit Ethernet. Gigabit Ethernet is backward-compatible with fast and 10-Mbps Ethernet, which connect more than 80% of networked desktops. AMD's GigaPHY-SD (Gigabit physical layer serializer/deserializer) and Vitesse's VSC7136 Gigabit Ethernet transceivers offer 1.25-Gbps data streams, transmitting data 10 or 100 times faster than Ethernet connections.

Both chips operate from single 3.3V power supplies, provide monolithic clock synthesis and recovery with no external components, and are suitable for coaxial and optical-link applications. They also both detect the "comma" characters that data-framing logic uses, and they accept 8B/10B encoded transmission data.

AMD based the GigaPHY-SD on the company's TAXI (transparent asynchronous transmitter-receiver interface) chip. It complies with the IEEE 802.3z draft standard for Gigabit Ethernet and typically consumes 700 mW of power. It also offers 5V-tolerant I/O pins, a 10-bit TTL interface, and a 125-MHz reference clock. Available in 64-pin packages that measure 10×10 or 14×14 mm, the GigaPHY-SD costs $23.50 (1000).

The VSC7136 has a 20-bit TTL interface and uses a 62.5-MHz reference clock that is half the frequency of the GigaPHY-SD's clock. The VSC7136 consumes 850 mW of power and has an automatic lock-to-reference function. The chip comes in a standard, 80-pin, 14×14-mm PQFP and costs $24 (10,000).

--by Beth Morrison

AMD, Sunnyvale, CA. 1-408-749-5703, www.amd.com.

Vitesse Semiconductor Corp, Camarillo, CA. 1-805-388-3700,
fax 1-805-987-5896.

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