October 23, 1997

Division by 10

Richard Sheldon lamented in Signals & Noise ("No fear of binary multiplication," EDN, Aug 1, 1997) that division by 10 was proving to be a stumbling block in his conversion of 64-bit binary numbers to ASCII decimal numbers. Such conversion is much easier if one converts the input number to a fraction first and then converts the fraction to decimal, starting with the most significant digit.

In Sheldon's case, this approach can be accomplished by multiplying (in hexadecimal) by 1.D83C_94FB_6D2A_ C34A. (This value is (2⁶⁴)/(10¹⁹).) The overflow digit from the multiplication is the most significant digit of the output. (The overflow is the integer part of (result/(2⁶⁴)).) To get each succeeding digit, multiply by 10. (The "overflow" is the output digit.) After 19 such multiplications, all 20 digits of the result have been output. The most significant digit is the first one out; the least significant digit is the last one produced by this algorithm.

To preserve accuracy, some care must be taken with the low-order 64 bits of the 128 (or so) resulting from the initial multiplication. I haven't worked out the requirements for Sheldon's application, but in my own application I keep a few "guard bits" on the low end in addition to the bits that are really of interest. After the first multiplication by 10, the need for those guard bits disappears. It may work out that rounding the result of the initial multiplication is sufficient to maintain accuracy and that no additional guard bits are necessary.

This process can be faster than repeated division, because multiplication is generally faster than division. The trade-off is that the intermediate results require manipulation of numbers slightly longer (that is, having more bits) than the number being converted.

If the 64-bit number represents a scaled engineering value, any required scaling factors can be folded into the initial multiplication factor. In addition, tricks can be played with that scale factor (for example, dividing it by 16) so there is no overflow, and output can be taken as the highest order nibble of the intermediate product or products. In general, guard bits are necessary to maintain 64-bit accuracy in these cases.

Larry Morris
via the Internet

DACs for DDS

Regarding "Give DACs due diligence for superior DDS performance" (EDN, July 17, 1997, pg 59):

I'm concerned with Bill Schweber's emphasis on glitches as "the largest sources of imperfection" in the dynamic performance of DACs. The emphasis on glitch is really a remnant of the video-DAC days, when a glitch in the DAC output manifested itself as a bright line on the video screen. In a DAC for frequency synthesis, a glitch that is constant with every transition (say, from clock feedthrough) represents a spurious tone at the clock frequency--a relatively benign effect in most applications. A glitch that has energy linearly proportional to the DAC output produces an effective gain error--also relatively benign. The problem arises from that portion of the glitch that is a nonlinear function of the DAC output. This nonlinearity generates harmonic energy that degrades the spurious performance. The DAC with the smallest glitch may or may not be the DAC with the most linear glitch.

Settling time is also a dangerous figure of merit to use. Linear settling produces bandlimiting but does not produce distortion or generate harmonics. Again, the nonlinear components of the settling are a concern. Integral nonlinearity and differential nonlinearity are fundamental measures of the linearity of the converter, and there is a strong correlation between these dc specifications and spurious-free dynamic range (SFDR) when synthesizing very low output frequencies. When synthesizing frequencies above 10 to 20 MHz, the dynamic nonlinearities of settling, asymmetric rise and fall times, and nonlinear components of glitch dominate.

Schweber's advice to characterize the DAC under the conditions identical to the final application is sound. Good SFDR performance for a single-tone, full-scale sine wave is not necessarily a good predictor of DAC performance in spread-spectrum or multitone applications.

David Robertson
Staff Design Engineer
Analog Devices
Norwood, MA

Corrections and updates

In the Design Idea "Use RS-232C port to measure pressure" (EDN, Aug 1, 1997, pg 104), Figure 1 is missing a 0.22-µF capacitor between the two dots that should connect to Pin 12 of IC_1D.

The contact information for Siemens Corp in "LVDS: power-miser angel, interconnect demon" (EDN, June 19, 1997, pg 85) has changed. The new information is: phone 1-201-256-6680, fax 1-201-256-6375, and e-mail peter_vanloo@sec.siemens.com.

Because of an editing error, "New IC packages really pack in the leads" (EDN, Sept 1, 1997, pg 93) contained some misinformation. The photo on pg 98 should have been attributed to Xynetix Design Systems, not Xilinx.

A photo in "Leading Edge" for Viewlogic Systems' Quiet Expert ("Get 'expert' help to locate pc-board EMI problems," EDN, Sept 12, 1997, pg 18) was inadvertently placed with another article in Leading Edge on pg 22 of the same issue. EDN apologizes for the errors.

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