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EDN
Hands-On Evaluation:
Has Wintel won the workstation war?
More and more workstation vendors are moving to Intel
mPs and Microsoft OSs, thanks to the cost advantage of the
high-volume PC business. This Hands-On report reviews a few
Wintel workstations, both from workstation-industry stalwarts
and from PC vendors moving into the high-end business.
--Maury
Wright, Technical Editor
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Tools
and techniques stifle EM emissions
Faster clocks, deep-submicron chips, denser boards, and
stricter government EMC regulations are forcing you to tighten
your pc-board designs. Using the right EDA tools and good
high-speed-board engineering techniques helps you design
EM-compliant systems.
--Jim
Lipman, Technical Editor
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Self-test
for FPGAs and CPLDs requires no overhead
By exploiting the reprogrammability of FPGAs and CPLDs,
you can create BIST logic that exists only during testing. As
a result, the test has no area overhead or performance
penalties to the normal system function.
--Miron
Abramovici, Bell Labs/Lucent Technologies, and Eric Lee,
Charles Stroud, and Mark Underwood, University of Kentucky
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To
create successful designs, know your
HDL simulation and synthesis issues
When creating HDL-based chip designs, you need to know
some techniques for developing well-structured and efficient
simulation and synthesis models. Coupling these techniques
with an understanding of simulation and synthesis runtime
issues provides the basis for good Verilog and VHDL designs.
--Douglas
J Smith, VeriBest
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Java
takes on C and C++
Java is hot. C++ programmers are turning to it in
droves. Is Java for you? Compare it to C++ and see.
--George
Ellis, Kollmorgen Corp
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In
picking ECCs, the key is bit-error location--not
rate
Bit-error-rate testing is a well-established measure of
digital-data-transmission quality. Even so, the location,
rather than the number, of errors in the data stream provides
the information you need to choose among the many ECC
strategies.
--Tom
Waschura, SyntheSys Research
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