November 20, 1997

Moving beyond programmable logic:
if, when, how?

Brian Dipert, Technical Editor

The decision to migrate from PLDs and FPGAs to lower cost ASICs seems easy at first glance but may be more complicated than you think. Do a little research and analysis before you proceed, and carefully choose which migration path to follow.

Congratulations! Your programmable-logic design exceeds target specifications, and the system it goes into is selling like hot cakes. You have no time to rest, though. The competition's breathing down your neck, and marketing says it has to cut prices. A midlife performance boost or power-consumption reduction would help, too. Your PLDs and FPGAs account for a large percentage of system cost, so purchasing wants to you to migrate the design to a cheaper, faster, lower power alternative.

At the same time, your managers--and you--are eager to begin defining and designing the next-generation system, with even more features. Should you focus your time and efforts on redoing the logic or work on the next project? Or, is there a way--aside from cloning yourself--that you can accomplish both objectives?

You have several available options for moving programmable-logic designs to ASIC-based alternatives. Although the end silicon implementation may essentially be the same, the money you spend, the time the conversion takes, the number of parts you must buy, and the amount of work you must do are key variables that differentiate the alternatives. Before deciding which option to pursue, research your own objectives, as well as those of purchasing, marketing, manufacturing, customer service, and other key organizations in your company.

Does conversion make sense?

Programmable logic is great for system development and early prototyping when you're working out the bugs in your design. However, PLD and FPGA benefits can extend to volume production as well. In the manufacturing line, one inventory of parts can service the needs of many systems. Just-in-time programming during board assembly or test allows customization to each end customer's requirements. All these capabilities, although perhaps hard to quantify, lower the system-manufacturing cost, and you lose these capabilities with ASICs.

But, it's conceptually cheaper to remotely reprogram a PLD or an FPGA than to send a technician to the customer site to take the system offline, dismantle it, and replace chips or boards. In-system-reprogrammable logic's benefits extend beyond manufacturing. With a floppy disk or memory card, serial or parallel connection, or even over a modem or wireless link, you can correct logic errors or add features even after the system is installed and operating at the customer site. The probability that your system will need an update varies from design to design and application to application. Also, practical limitations, such as the inability to pin-lock your design or maintain timing from one revision to another, may preclude such a scenario.

Programmable-logic-chip costs have significantly decreased over the last few years; for densities of tens of thousands of gates or more, prices closely approximate those of gate-array ASICs. At advanced process lithographies, the die size necessary to incorporate a given device pin count's bond pads may be larger than the amount of silicon needed to satisfy a target gate count (Figure 1). This characteristic, "I/O bounding," means that, up to a certain gate-count density and pin count, gate arrays and programmable logic have equivalent die sizes.

Die size--along with volume, test costs, and other secondary factors--is a key element in price. PLDs and FPGAs targeting gate arrays include Actel's MX, Altera's FLEX6000, QuickLogic's pASIC3, and Xilinx's XC5200. Gate arrays are moving to esoteric packaging and multiple rows of bond pads to forestall I/O bounding. These developments may delay, but ultimately won't prevent, cost convergence with programmable-logic alternatives. A growing programmable-logic market targeting the demise of gate arrays along with upcoming FPGA-plus-ASIC combinations were key factors in Actel's decision to phase out its mask-programmed-logic product line, according to Director of Product Marketing Robert Nalesnik.

ASIC vendors often charge NRE fees, which can reach tens or even hundreds of thousands of dollars. You also must buy a minimum quantity of parts in either units or dollars to satisfy the vendors' business criteria. This minimum quantity has increased over time, because advanced lithographies allow ASIC companies to squeeze more gates on each die and more die on each wafer. The per-unit cost differential between a PLD or an FPGA and a gate-array alternative depends on how many parts you contract to buy.

Today, your marketing peers may predict that they can sell hundreds of thousands of systems over a multiyear production life. ASIC NRE charges and minimum volume requirements have a more significant cost impact, however, if you end up selling only a few thousand systems and the production run ends within a year. Minimum volume requirements are especially cost-damaging if you have to discard unused ASIC inventory because of product obsolescence or logic errors. For this reason, some companies, even if they migrate from programmable logic to gate arrays for volume production, convert back to PLDs or FPGAs near the end of their products' life.

Don't underestimate the design time, effort, and cost you'll incur in completing the conversion. Minimally, you often need to analyze and approve your vendor's simulation results and characterize prototypes in a large end-system sample set to convince yourself that a gate-array design is robust. Regardless of the conversion option, the overall flow is the same (Figure 2). The less NRE you pay to the vendor you select and the lower the per-unit cost you negotiate, the more work you may need to do.

Balance the cost of a redesign against the opportunity cost of working on your next project. Both programmable-logic and gate-array vendors provide documentation and programs on their Web sites that help you with this analysis. Realize, though, that each company has its own preference about what your decision should be: to stay with programmable logic, to migrate to a mask-programmed part, or to migrate to a gate array. The assumptions that the companies' application notes and utilities make reflect this bias. Closely examine these presumptions before trusting the results, and consider using analysis tools from multiple vendors to give you additional perspective.

Standard ASIC conversion

Given these qualifiers, instances still occur in which the economics favors a conversion. According to Xilinx's Sandeep Vij, vice president of marketing, almost all design starts having fewer than 20,000 gates stay with programmable logic, whereas the decision for designs with 20,000 to 50,000 gates hinges on anticipated volume. However, for designs having more than 50,000 gates, you'd better have a conversion plan, according to Vij. Note that, just a few years ago, these gate-count ranges were an order of magnitude smaller than today, and they'll continue to grow. Most programmable-logic conversions are to gate arrays rather than to standard cells, embedded ASICs, or full-custom ASICs, because these alternatives are usually economical only in very complex or high-volume designs.

The minimum business that a high-volume gate-array vendor usually considers is approximately $250,000. In this era of multimillion-gate ASICs, you often find the conversion cost savings to be greatest if you can integrate multiple PLDs or FPGAs into one ASIC. Additionally, you might also be able to include memory and datapath functions, such as DSP and CPU cores and FIFO buffers, as well as simple analog functions. Expect to spend more time on the design conversion to achieve this goal, though; faster internal signal paths will replace slow external chip-to-chip delays, increasing the potential for asynchronous timing problems. For this reason, combining programmable-logic chips that interact only minimally or not at all with each other into one ASIC will provide the most effortless transition. On the other hand, minimal interaction implies a greater number of I/O buffers, increasing ASIC cost.

Standard ASIC conversions can provide benefits besides multichip integration. For example, these conversions typically provide greater choice of output buffer types and strengths. ASICs also offer greater pinout flexibility, and you might even be able to reduce the pin count to less than that of the PLD or FPGA. You can even add built-in self-test to speed chip testing. On the other hand, you cannot use some specialized circuits that programmable-logic vendors provide you unless you re-create them from generic gate-array, two-input NAND gates. You might also need to redesign the system board if the replacement chip doesn't exactly mimic the original PLD or FPGA black-box characteristics--in its I/O-buffer drive, slew rates, ESD, input-threshold behavior, or power-up configuration protocol, for example--or isn't available in a footprint-compatible package.

With programmable logic, routing-timing delays often exceed logic-throughput delays, especially in FPGA architectures in which short routing lines dominate and those without dedicated networks for clocks, carry chains, and other performance-critical signals. ASICs provide more robust routing resources and lack programmable logic's high-impedance routing connections, such as antifuses and pass gates. Therefore, ASICs usually deliver both higher performance and lower power, although with sub-0.5-µm lithographies, routing is also becoming a significant percentage of total ASIC propagation delay.

Because a vendor treats a standard ASIC as a new product, the company guarantees any timing or power improvements you achieve. Higher gate-array performance is both a blessing and a curse, however, in that it can wreak havoc on asynchronous circuits. If you complete a programmable-logic design in a way that doesn't adapt well to conversion, you may need to redo the design from scratch (see box "Designing with conversion in mind"). If this is your first ASIC design, the new tool and process learning curve can be daunting, and the probability of first-time success is low. The more design turns you need, the more time the conversion takes, and the more money you may have to pay.

ASIC vendors expect you to give them a fully routed netlist that you create using their libraries and that you verify with extensive postlayout simulation. Test-vector development can consume a significant percentage of design time, especially for programmable-logic designers who follow the controversial but widespread practice of doing no simulation but simply reiterating the design until it works. Functional test vectors validate that the logic you designed works as you intend but often provide low overall node-test coverage. Low coverage is OK for many PLDs and FPGAs, because the manufacturer can fully test EPROM-, flash-, and SRAM-based programmable-logic devices before shipment.

With ASICs, however, as with antifuse FPGAs to a smaller degree, your testing must catch both functional errors and semiconductor-processing defects, such as stuck-at-0 and stuck-at-1 faults. If the design requires scan circuits for automatic test-program generation (ATPG) to boost test coverage, you must add them, and scan logic might radically impact resultant logic function, timing, and required gate count (Figure 3). One advantage of ATPG, though, is that a design often requires a smaller vector set to test counters and other sequential circuits than does a functional vector-set alternative.

Conversion services

Several companies not only are mainstream ASIC vendors, but also provide programmable-logic-conversion capabilities as part of their value-added services portfolio (Table 1). Once you give them a programmable-logic netlist, these vendors within weeks convert it to a gate-array counterpart. After usually completing a joint design review of postlayout simulation results, they deliver prototypes in a few weeks. After you approve the prototypes, volume production units follow in a few weeks or months. You can sometimes even skip the prototype stage if you're in a hurry and go right from simulation to volume production. This option shaves some time off the overall schedule but increases risk, and you have to pay for the chips whether or not they work.

In an ideal scenario, the netlist conversion and simulation processes are highly automated, and the vendor can quickly return results to you for analysis. Device gate count, pin count, speed, and overall design complexity are key regulators of throughput time, however. Conversion vendors claim that, given enough time and money, they can re-create the functions of most programmable-logic, vendor-proprietary circuits, but you must tell them up-front that you used these circuits. When evaluating vendors, read the fine print, because not all are willing to tackle every capability of each programmable-logic chip. American Microsystems Inc's (AMI's) Vince Hopkin, business unit manager, states that all of the more than 1000 conversions that his company has accepted over the last eight years were ultimately successful. Other companies claim hundreds, if not thousands, of successful conversions, ranging from the smallest SPLDs to the largest FPGAs. Temic Semiconductor's Universal Logic Circuit (ULC) product marketing manager, Carolyn Russell, quotes a greater-than-90% first-time functional success rate and greater-than-99% success after one design turn, which usually involves timing optimization, not logic fixes.

If your design is fully synchronous, some conversion companies waive the requirement for functional test vectors, and all add scan-test flip-flops to the gate-array netlist if necessary for high ATPG coverage. However, only a few programmable-logic designs fit into the "fully synchronous" category. Fortunately, the vendors report that the widespread availability of low-cost programmable-logic tools is increasing the percentage of conversions they see that include at least some simulation results. Some companies can even translate automatic-test-equipment vectors and captured logic-analyzer waveforms into ASIC-test vectors. Ensure that the vendor can handle your preferred netlist and simulation file formats before you proceed. Conversion companies are also working on asynchronous ATPG capability, which they hope to begin offering in mid-1998.

You also need to specify any critical timing paths when you submit your purchase order, which can be an especially difficult task if you did your original design in an HDL. Conversion includes prelayout and postlayout test-vector simulation and static-timing analysis, both to check critical timing paths and to ensure sufficient setup-and-hold times for all device flip-flops to avoid metastability problems. So-called five-corner simulation (also known as "four-corner" simulation by vendors that use but do not explicitly highlight the typical variable set) refers to testing at worst-case voltage and temperature extremes, repeated at each of the following manufacturing-process parameters:

• Fast N-type transistors, slow P-type transistors;
• Fast N-type transistors, fast P-type transistors;
• Slow N-type transistors, fast P-type transistors;
• Slow N-type transistors, slow P-type transistors; and
• Typical N-type transistors, typical P-type transistors.

Because conversion vendors understand the programmable-logic architecture they're trying to mimic but not your circuit implementation within it, expect to get at least a few phone calls during the conversion. Hillol Sarkar, strategic marketing manager at S-MOS Systems, has an interesting perspective on programmable-logic expertise. His company also offers cores it develops in-house to its ASIC customers. S-MOS first internally prototypes these cores in Xilinx or, where performance is critical, Actel FPGAs. During this development, the company's engineers obtain extensive FPGA knowledge, which they subsequently apply to conversions.

Minimally, a conversion vendor guarantees that the gate-array input-to-output timing and power consumption are at least as good as those in the original PLD or FPGA. If your design can't tolerate faster timings, the vendors add the necessary delay circuits within the chip. Be prepared for a redesign down the road when the ASIC manufacturer moves to a different process, however. Fortunately, because of inherently faster routing delays, ASICs usually need not match the advanced lithographies of the original programmable-logic device, although sub-10-nsec PLDs can be a challenge. If one of your intentions in the conversion is to achieve higher performance or lower power, your list of potential conversion partners becomes shorter, because not all are willing to do the extra characterization to guarantee your improved results. Performance improvements are generally easier to predict, test, and, therefore, guarantee than power savings.

Approximately 20% of AMI's conversion business involves combining multiple PLDs and FPGAs into one ASIC, and Atmel, Orbit Semiconductor, S-MOS Systems, and Temic Semiconductor provide similar integration support. In these cases, the vendor first converts each programmable-logic netlist to its gate-array counterpart. Then, the company tackles the additional work of combining each module via a high-level schematic, creating necessary test vectors, and resolving any problems resulting from the migration from slow chip-to-chip to fast on-chip timings. Just as with standard ASICs, this integration can also include discrete memory, processor cores, and even simple analog functions. However, expect to pay a higher NRE fee or guarantee more business than a standard one-for-one conversion requires.

Temic Semiconductor's ULC program is relatively unique among conversion companies for several reasons. First, Temic, along with S-MOS Systems and Clear Logic, requires no up-front NRE fee, although the company expects you to commit to a minimum order size if the gate array works as Temic promises. In exchange, the company requires a comprehensive up-front understanding of your PLD or FPGA design, including any proprietary programmable-logic circuits that you might use, to assess the probability of a successful conversion. Also, the design review after conversion and before prototypes is optional. Russell states that, assuming that your design passes the up-front analysis step and that Temic agrees to take the business, the company is confident enough of first-time success that it doesn't burden you with additional unnecessary review unless it will increase your confidence.

Some distributors promote design-conversion assistance from field application engineers as one of their services. A new entry to the list of design-conversion-service vendors, Clear Logic makes some aggressive claims: no NRE fees, no minimum-order quantities, no test vectors, 100% compatibility with the original CPLD or FPGA, guaranteed power-consumption reductions, one to two weeks to prototypes and two weeks from approval to volume production. Details on just how Clear Logic plans to meet these timing goals are unfortunately not public, although the company plans to release more information in early 1998 when it will begin shipping products.

Conversion vendors tailor their services for programmable-logic designers, who typically require lower volumes and lower gate counts and have less experience with ASIC tools and development processes. You don't generally obtain as low per-unit cost as you would get from a high-volume ASIC vendor, especially one that uses cell-based, embedded, or full-custom ASIC technology. However, up-front NRE fees are lower, the minimum business requirement is smaller, and the amount of vendor involvement is greater.

This trend continues with mask-programmable-logic devices, which you obtain from your PLD or FPGA manufacturer (Table 1). Pricing information throughout this article comes from general comparisons from vendors' "typical-customer" data. Your actual negotiated price depends on how much a company wants your business and also varies with factors such as how heavily loaded with other products the company's fabrication lines are. Find out in advance whether your conversion-service and mask-programmable-logic vendor charges an additional "respin" fee if the first or a subsequent conversion doesn't work.

Xilinx's HardWire product line supports the company's XC2000, XC3000, XC4000, and XC5200 FPGAs but not PLDs. Xilinx also requires no test vectors, and you don't need a netlist; Xilinx accepts a configuration bit-stream file. This minimum requirement is ideal for poorly documented designs or if the engineer who developed the design is busy on another project or has left your company. Xilinx's XH3 FpgASICs, introduced in October, are the third generation of HardWire devices. Instead of resynthesizing the FPGA netlist into a generic gate-array counterpart, Xilinx remaps the netlist to configurable-logic-block-compatible circuits that the company constructs on a sea-of-gates ASIC core.

Both the HardWire logic blocks and the interblock routing nets are in comparable physical locations on the ASIC die to those on the FPGA (Figure 4). Xilinx's goal is to avoid any change in the relative timing between signals, although absolute timings usually get faster for all signals. XH3 parts also include dedicated circuits that exactly emulate the JTAG, power-on reset, configuration emulation, and other behavior of the FPGA. FpgASICs also provide necessary FPGA-compatible I/O buffers and embedded memory. If any problems with the HardWire units occur, whether Xilinx's or the customer's fault, the company ships FPGAs at reduced prices while redoing the HardWire version.

Altera's MPLDs (masked PLDs) and Lucent Technologies' MACO (masked array conversion for optimized reconfigurable-cell array, or ORCA) take a more conventional programmable-logic-to-generic-gate-array resynthesis route. Altera recently announced its ability, which it developed with foundry partner TSMC (Hsin-Chu, Taiwan), to support conversions of Altera's product line to MPLD counterparts. However, as Senior Product Marketing Manager Sunil Baliga points out, aggressive PLD cost reductions and other factors make MPLD migrations economically practical for only the highest volume or highest gate-count Altera PLDs. After running the PLD design through the Design Doctor design-rule-checker (DRC) utility that comes with Altera's Max-Plus II, an MPLD customer submits the netlist to Altera, which reruns the DRC and helps to correct any problems, such as asynchronous clocks or race conditions, before completing and validating the conversion.

Lucent uses a proprietary mask-configurable, cell-based technology, the same process the company uses in its ASICs. Marketing Manager Barry Britton estimates that Lucent has completed more than 30 conversions, spanning both the ATT3000 and the ORCA 2C/2T product families, in the two years that the MACO program has been in place. Lucent uses the customer's ORCA Foundry design files, which contain detailed layout and timing information, to guide conversion. The company accepts vectorless designs only if it understands the internal clocking scheme. Lucent even provides the ability to represent all worst-case process "corners" not only in simulations but also in prototype units--even in a small sample--by varying transistor dimensions and other characteristics across a single semiconductor wafer.

Both Britton and Xilinx HardWire Division General Manager Chuck Fox stress the importance of their companies' in-depth knowledge of the FPGA's behavior in creating the masked alternative. With output buffers that automatically float during power-up and configuration handshaking pins that toggle from low to high just as in the original, for example, you need not redesign anything else in your system.

QuickLogic calls its mASICs masked, yet they are the same products as the company's antifuse FPGAs. Their 100% silicon compatibility with the FPGAs eliminates any compatibility concerns and the need for test vectors, but provides no higher performance or lower power than the FPGAs. The mASICs are the company's cost-reduction path for the highest volume customers, and QuickLogic programs the mASICs from your place-and-route output file during in-factory testing.

ICT also advertises masked versions of its PEEL SPLDs on its Web site, and WaferScale Integration and its foundry, AMI, can both deliver masked members of the PSD3xx, PSD4xx, and PSD5xx product families on request, with PSD6xx and PSD7xx devices to follow next year.

If you choose the mask-programmable-logic-device path for cost reductions, you may find that it will require the least amount of work and the highest probability of 100% form, fit, and functional compatibility. Because the programmable-logic vendor is eager to retain your business, your negotiating power is strong, especially if you need to obtain programmable devices at reduced prices because of a problem with the conversion. However, the vendor doesn't usually guarantee any performance or power improvements over the PLD or FPGA and offers no ability to integrate multiple chips into one ASIC alternative. Finally, a mask-programmable part can be as much as twice the price of an alternative device from an ASIC vendor.

References

1. "Conversion information and order forms," Altera Corp.

2. "Vectorless FPGA to ASIC migration," American Microsystems, 1997 Design SuperCon: On-Chip System Design Conference.

3. "Converting FPGAs and PLDs to Atmel gate arrays," Atmel Corp.

4. "Masked array conversion for ORCA manual," Lucent Technologies.

5. "Designing for conversion to gate arrays," Orbit Semiconductor.

6. "Good design practices," Temic Semiconductor.

7. "The Ten Commandments of excellent design," Part 1, Electronic Design, April 1, 1997, pg 33.

8. "The Ten Commandments of excellent design," Part 2, Electronic Design, April 14, 1997, pg 123.

9. "FPGA design considerations for HardWire designs," Xilinx Corp.

Acknowledgments

Bill Ewing from IMX Technologies (Arlington, VA) and Stefan Heinzmann shared their ASIC-design and programmable-logic-conversion experiences with me and provided valuable hands-on information on the rewards and pitfalls of various alternatives. Thanks also to Debora Grosse from Agate Technology (Decatur, GA) for her feedback.

You can reach Technical Editor Brian Dipert at 1-916-454-5242, fax 1-916-454-5101, e-mail edndipert@worldnet.att.net, http://members.aol.com/bdipert.

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