November 20, 1997

Filter cutoff tracks ADC conversion rate

Kevin R Hoskins, Linear Technology Corp, Milpitas, CA

The circuit in Figure 1 matches an antialiasing filter's cutoff frequency to an ADC's changing conversion rate. Two main design requirements are high efficiency and the ability to convert signals with varying bandwidths. To help conserve power, the circuit uses a low-power switched-capacitor filter and an ADC whose power consumption decreases as its conversion rate decreases.

The ability to change an antialiasing filter's cutoff frequency, F_C, is important when an ADC uses different conversion rates to convert analog signals. If you use a fixed-frequency filter, you'll have a tough time choosing the right cutoff frequency. For example, if you set the cutoff to handle the highest conversion rate, the cutoff may be too high when the conversion rate goes down. This situation can lead to input frequencies with sufficient energy to cause aliasing. Conversely, if the filter's cutoff matches the lowest conversion rate, the cutoff may be too low and limit valid high-frequency information that is below the Nyquist frequency of the ADC.

The circuit in Figure 1 uses an eighth-order, progressive, elliptic, lowpass switched-capacitor filter, IC₁, to limit the input signal's bandwidth. This filter can attenuate signals by 70 dB at 2×F_C. The host processor generates the clock that controls the filter's cutoff frequency. IC₃ derives the conversion clock for the ADC, IC₂, by dividing the filter's clock by 2. For this design, the master clock is 400 kHz, so the ADC clock is 200 kHz.

The host processor requests a conversion by asserting a logic low on the CHIP SELECT line, which connects to the CS/SHDN input pin of the ADC. When CS/SHDN is a logic low, the ADC takes 15 clock cycles to generate conversion data. The host processor must assert a logic high on the CS/SHDN pin for at least 2 µsec before the start of the next conversion.

The maximum serial-clock frequency of 200 kHz for the ADC sets the maximum conversion rate at 12.5k samples/sec. With this conversion rate, the maximum input signal that the ADC can convert without causing aliasing errors is less than 6.25 kHz. The filter's cutoff frequency is a compromise between maximum attenuation at twice the sampling frequency and ensuring that the filter's passband is sufficiently wide. The circuit achieves this compromise by running the filter clock at the master-clock frequency of 400 kHz, which is twice the frequency of the ADC's conversion clock. The ratio of the filter's cutoff frequency to its CLK input at Pin 5 is 1-to-100. Thus, F_C=400 kHz/100=4 kHz, which is also equal to one-fiftieth of the ADC's conversion clock. The filter's input network sets a highpass cutoff of 3.1 Hz.

Figure 1 shows an optional passive-RC lowpass filter between IC₁'s output and the ADC's input. Relative to a 2V p-p output signal, the magnitude of any residual clock signal from this filter is ­80 dB. However, the residual clock signal's magnitude remains constant, independent of the output signal's magnitude. Therefore, using the simple passive-RC lowpass filter further attenuates clock-signal feedthrough. The cutoff frequency of this passive filter is not critical, but you should set it to at least one octave above IC₁'s maximum expected cutoff frequency. The values in Figure 1 set the cutoff frequency for the passive lowpass network at 8 kHz.

One area that requires attention is filter settling time. When a filter's cutoff frequency changes, a minimum amount of time has to elapse before the output settles to within a given error band. IC₁'s eighth-order elliptic filter requires 13.5/F_C to settle within a 12-bit-resolution error band, so the filter requires 13.5/4 kHz, or 3.4 msec, to settle. Once the filter settles, the ADC can begin generating conversions. At a cutoff frequency of 100 Hz, the filter's settling time is 135 msec. (DI #2115)

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