November 20, 1997

Circuit takes square root of input voltage

Mark Shill, Burr-Brown Corp, Tucson, AZ

For an NMOS transistor operating in the saturation region, the relationship between the drain current, I_D, and the gate-source voltage, V_GS, is governed by the square-law equation

(1)

where V_T is the threshold voltage and µ_N, C_OX, L, and k are constants not relevant to the square-law relationship.

You can algebraically manipulate Equation 1 to yield the gate-source voltage as a function of the drain current:

(2)

where I_D is the drain current.

By using the transfer function of Equation 2, you can make a circuit take the square root of an input voltage. Such an implementation uses an NMOS transistor to obtain the square root of a positive input voltage, V_IN (Figure 1). The op-amp gain stage using IC₁ inverts V_IN; the inversion is necessary because of the polarity of the I_D flow in MOSFET Q₁. If you configure op amp IC₁ for a gain of ­1, the drain current of Q₁ becomes I_D=V_IN/R₃.

Q₁ is an SD215 enhancement-mode n-channel MOSFET from Siliconix (Santa Clara, CA). It connects in the feedback loop of op amp IC₂ such that IC₂'s output voltage biases Q₁'s gate in relation to drain current I_D. The body terminal of Q₁ connects to the source terminal to eliminate any back-body voltage effects. Diode D₁ provides feedback and clamps the output of IC₂ when V_IN¾0V and Q₁ turns off. Because the inverting terminal of IC₂ is at a virtual-ground potential, the output voltage of IC₂ is in effect the gate-source voltage, V_GS, of Q₁. Thus, substituting I_D=V_IN/R₃ into Equation 2, the output voltage of IC₂ assumes the relationship

(3)

To eliminate the first radical term and V_T from Equation 3, the output voltage of IC₂ connects to an INA118 instrumentation amplifier. The negative-input terminal of the INA connects to a bias level of approximately 1V, approximating the MOSFET's threshold voltage, V_T. The gain of the INA is ˆR₃·k, or approximately 6 V/V. The gain of the INA118 is 1+50k/R_G, where R_G is an external gain-setting resistor. A 20-kilo-ohm, 20-turn potentiometer provides both sufficient range and resolution.

To calibrate the square-root circuit, first vary V_IN between two accurate voltage levels, such as 9 and 1V. Then monitor V_OUT and adjust the gain-setting resistor, R_G, until the corresponding peak-to-peak output voltage, V_OUT, is equal to ˆ9V­ˆ1V=2V. Finally, adjust the offset voltage using potentiometer R₅ such that V_OUT=1V for V_IN=1V. Transistor Q₁ begins to operate in the subthreshold region for input voltages lower than approximately 1V and thus no longer follows the square-law equation. Therefore, V_OUT can drop off quickly and even become negative for low input-voltage levels.

Once the voltage output of IC₂ approaches the threshold voltage set by R₅, the output voltage of the INA118 approaches 0V. As the output of IC₂ becomes less than the threshold voltage, V_T, for low Q₁ drain current, the INA's output becomes negative. The addition of diode D₂ and resistor R₇ improves low-voltage performance. As Q₁ enters the subthreshold region and the INA's output pulls toward 0V, diode D₂ forward-biases and lowers the threshold voltage set at the INA's negative input. This addition improves the square-root transfer function for input voltages of 0.5 to approximately 1V.

For input voltages of 0.5V to 10V, the maximum error is 70 mV (Figure 2). If you use a reduced input-voltage range, you can further improve the square-root accuracy by calibrating over the reduced-range endpoints. To prevent the output response from going below 0V for input voltages lower than 0.5V, connect the optional clamping circuit in Figure 3 to the INA118's output.
(DI #2111)

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