November 20, 1997

WHAT'S HOT IN THE DESIGN COMMUNITY

30V MOSFETs drive R_DS(ON) to 4 mV

By implementing a proprietary 32 million-cell/in.² TrenchFET technology, Temic Semiconductor's n-channel MOSEFTs can handle 75A at 30V with maximum on-resistance of 4 mega-ohms. The low on-resistance reduces voltage loss and power dissipation and eliminates the need for designers to parallel multiple devices to achieve comparable performance, the customary approach in many applications. Applications for these 30V devices include automotive and industrial controls, such as heating, ventilation, air conditioning, fans, alternators, and motors.

These devices are available now, and a presentation at next month's IEEE International Electron Devices Meeting in Washington will discuss the underlying process of these MOSFETs. Low-impedance avalanche diodes throughout the MOSFET's die provide critical voltage clamping and essential device protection. The SUP75N03-04, which comes in a TO-220 package with free-air thermal impedance of 62.5ºC/W, and the SUB75N03-04, in a D²PAK package with pc-board-mounted thermal impedance of 40°C/W, cost $4.36 (100,000).

--by Bill Schweber

Temic Semiconductors, Santa Clara, CA. 1-408-567-8220, fax 1-408-567-8995, www.temic.com.

Mobile graphics accelerators integrate DRAM

Two new mobile graphics accelerators from S3 and Silicon Motion integrate DRAM, thus cutting the cost, power consumption, and real estate necessary for a graphics subsystem.

The ViRGE/MXi from S3 integrates the company's S3RAM DRAM with a custom 128-bit-wide array for in-creased memory bandwidth. The average power consumption with 2 Mbytes of integrated S3RAM and running DOS is about 750 mW. The accelerator provides 2- and 3-D performance, improved power management, Duo-View for dual displays, and Macrovision copy protection for digital video disks (DVDs). Duo-View technology supports the Windows 98 multimonitor interface and enables notebook users to display images simultaneously on separate monitors or the same image on any LCD or CRT monitor. Macrovision modifies the analog-TV-output signal, enabling users to view DVD content on a TV while preventing users from taping DVD content with a VCR. The part is pin- and software-compatible with the previous ViRGE/MX, which became available in April. The ViRGE/MXi accelerator is available for sampling now in 208-pin BGA packages and costs $54 (10,000).

The other accelerator, the LynxE from Silicon Motion, joins the company's Lynx family. It integrates 2 Mbytes of DRAM and uses a 192-bit-wide memory architecture for data rates as high as 1.8 Gbytes/sec when you expand it to use external DRAM along with the integrated DRAM. Silicon Motion estimates the average power consumption will be less than 500 mW because of dynamic power management and patented VirtualRefresh.

The LynxE includes dual-display capability, 2- and 3-D performance, MPEG2 and DVD playback, video capture, and screen rotation. The dual-display feature allows you to view two applications with independent resolution and refresh rates on LCDs, CRTs, or TVs using Windows 95 or NT. You can also switch on the fly from landscape to portrait modes. The LynxE will be available for sampling next month. It will come in 256-pin BGA packages and cost $42 (1000).

--by Stephen Kempainen

S3 Inc, Santa Clara, CA. 1-408-588-8000, fax 1-408-980-5444, www.s3.com.

Silicon Motion, San Jose, CA. 1-408-467-9388, fax 1-408-467-9390, www.siliconmotion.com.

1/4-in. display has 1/4-VGA resolution

The CyberDisplay from Kopin measures only 1/4 in. diagonal, but its active-matrix LCD structure provides a resolution of 320×240 pixels. When you magnify the image with the company's 19× 16-mm lens, the optical image is equivalent to that of a 20-in.-diagonal desktop monitor. In addition to accepting standard full-motion video data, the display can operate with NTSC, PAL, and SECAM TV formats. The device consumes less than 30 mW of power.

Kopin offers several demonstration and development packages for display designers. The $495 CyberDisplay Developers' Kit contains the optical engine (display, backlight, and lens), a driver board, a power supply, video cable, and applicable literature. The $750 CyberDisplay Demonstration Tool includes a handheld viewing device that incorporates the same components as those in the Developers' Kit. You can plug the Demonstration Tool into a VGA output for viewing. The CyberDisplay, including the backlight and lens, costs $75 (sample quantities).

--by Bill Travis

Kopin Corp, Taunton, MA. 1-508-824-6696, fax 1-508-824-6958, www.kopin.com.

Detachable batteries remove SRAM deficiencies

Dallas Semiconductor's PowerCap package eliminates two drawbacks of monolithic battery-backed SRAMs: poor high- temperature tolerance and costly re-placement. Because reflow-soldering temperatures can exceed 220°C, whereas lithium batteries are rated to only 85°C or so, designers have historically used large DIP-packaged parts, in-stalling the memories after soldering the socket on the board. When the nonrechargeable batteries eventually failed, you had to replace the entire memory, even though the SRAM was still functional. The alternative, a standard SRAM with separate controller IC and battery, required a much larger board footprint.

The PowerCap package combines a surface-mountable base (containing the memory and controller) with a cap containing the battery. After soldering the base onto the system board, the battery snaps on top. Battery removal and re-placement requires only a small screwdriver. The 34-pin package measures 0.25 in. high and has a footprint measuring less than 1 in. sq. Gold-plated contact points on the base and cap ensure reliable electrical connections. SGS-Thomson's (Lincoln, MA) SnapHat package is conceptually similar.

Dallas Semiconductor offers the PowerCap on 10 devices from three product families: the 12 series nonvolatile SRAMs, the 13 series with monitoring circuits for battery and system power, and the 164x series with an integrated real-time clock. For example, the DS1230YP-100 costs $6.62 (10,000), and the DS1-330YP-100 costs $7.58 (10,000); you'll also need the DS9034PC battery cap at $3 (all quantities). The DS1644P-150 costs $13.18 (10,000); the required DS9034PCX battery cap also includes a crystal oscillator and costs $4.38 (all quantities). SRAM densities range from 64 kbits to 4 Mbits, all at commercial temperature. The company plans to offer extended-temperature versions in early 1998.

--by Brian Dipert

Dallas Semiconductor, Dallas, TX. 1-972-371-4000, fax 1-972-371-3717, www.dalsemi.com.

DC/DC converter seamlessly steps up and down

It's a tough regulator-design problem when your dc source varies both above and below your desired output value. The LTC1514 and LTC1515 from Linear Technology ease the challenge, though. Each SO-8 IC produces 3.3 or 5V output (depending on version) from an input than can range during operation from 2 to 10V, such as a three-cell alkaline pack (4.5V when new and 2.7V when dead) sourcing a 3.3V rail. The LTC1515 also allows a user-settable output voltage. The converters do a bump-free switch from step-down to step-up mode as needed. These 650-kHz-switching-frequency devices need just three capacitors and no inductors.

Output current can be as high as 50 µA, typical operating current is 60 mA, and standby current is 10 µA for the LTC1514, which also includes a low-battery-detector output. The LTC1515 dispenses with the output indicator but lets you disconnect the load from the input voltage and has a shutdown supply current lower than 1 µA. Both parts, which cost $3.50 (1000), incorporate short-circuit and overtemperature protection as well as soft start to limit the inrush current at power-on.

--by Bill Schweber

Linear Technology Corp, Milpitas, CA. 1-408-432-1900, fax 1-408-434-6441, www.linear-tech.com.

Get capacitors online

Time Electronics recently announced Capacitors Online, an Internet-based service at www.time.avnet.com/caonline/ca.htm. The page lets you access Time's franchised manufacturer capacitor inventory, including products from AVX, Mallory, Murata, Nichicon, Philips, Roederstein, Vishay/ Sprague, UnitedChemi-Con, and Vitramon. Using the service, you can build capacitors by entering the specifications they need. The system's graphical user interface also provides searches by part number, which draw from a database of thousands of capacitors. Time also offers Connectors Online and plans to offer online services for military connectors, resistors, switches, relays, fans, and motors.

--by Fran Granville

Time Electronics, Peabody, MA. 1-978-532-9736, fax 1-978-532-9955, www.time.avnet.com.

Digital BIST cells boost mixed-signal-chip testing

Early next year, LogicVision will begin offering a technique for testing embedded analog blocks in digital chips. Using new built-in self-test (BIST) blocks, the company will provide a service for implementing chip-level mixed-signal testing that you can use with digital automated test equipment (ATE). This mixed-signal test capability comprises small BIST blocks that you get as synthesizable Verilog or VHDL code. Embedding these blocks on your mixed-signal chip provides a way to digitally test analog-chip functions, sometimes eliminating a need for analog ATE.

The first blocks available from LogicVision are adcBIST and pllBIST for testing ADC and PLL functions, respectively. Each BIST cell takes about 1000 logic gates. For ADC tests, you use the adcBIST block, a linear RC network either on- or off-chip and a 0.1- to 100-MHz sampling clock. With adcBIST, you can measure offset, gain, second- and third-harmonic distortion, and rms idle-channel noise, all at-speed, for 6- to 16-bit ADCs. You can't use the adcBIST cell for sigma-delta ADCs. You use the pllBIST cell with an input multiplexer for both analog and digital PLLs to test lock range, lock time, loop gain-bandwidth, and jitter. PLL test time is 10 msec or less for clock frequencies greater than 10 MHz.

You do both ADC and PLL testing synchronously and can control the tests with a standard boundary-scan (IEEE 1149.1) test-access-port controller. The adcBIST and pllBIST blocks come in different configurations, allowing you to implement a range of testing from simple parameter measurements through comparison of measured results against predetermined pass/fail limits. The BIST blocks are now available only as part of a service contract; the cost depends on your requirements and schedule. Typical prices for first-time customers start at around $50,000.

--by Jim Lipman

LogicVision, San Jose, CA. 1-888-584-2478, fax 1-408-467-1180, www.logicvision.com.

Tool suite hurdles design-domain boundaries

By combining old and new software products, Precedence is now providing a means of performing multidomain system simulation. Multidomain simulation means concurrent analysis of multiple system parameters--electrical, thermal, mechanical, and so on. This capability lets you more accurately verify total system performance, including parameter interaction across domain boundaries. Examples of these interactions include phenomena such as mechanical-clutch self-heating and motor torque as a function of drive current.

A multidomain simulation system comprises the SimPrism multisource partitioner, the SysMatrix simulator backplane, and domain-specific simulator matrices, or "blocks," that plug into the SysMatrix backplane and accept interface software to third-party simulators for a domain. SimPrism lets you describe your system concurrently using different domain sources, such as a VHDL model of a µC and a finite-element model of a motor. The software then creates appropriate subrepresentations of the design for each client simulator you specify and lets the subrepresentations communicate to provide a multidomain simulation environment.

Precedence now offers four simulator matrices. You use SimMatrix for analog and digital electrical simulation and with discrete-event simulators, such as Spice- and HDL-simulation tools. EMMatrix, for electromechanical simulation, works with time-continuous physical phenomena, such as inertia, torque, and temperature gradients. Simulation in this matrix is based on finite-element analysis. For software simulation and hardware/software co-verification, Soft-Matrix accepts instruction-set and cycle-accurate simulators. The transaction-based simulation works on an interrupt-driven communication model. RFMatrix for simulation in the RF domain is based on a sampled-waveform model and transient representation of modulated high-frequency signals.

The SimPrism partitioner and SysMatrix backplane cost $8000 each. Each domain-specific simulator matrix costs $2000. In addition, you pay $2000 for each interface between a simulator matrix and third-party simulator. Simulator prices vary according to product and vendor.

--by Jim Lipman

Precedence, Campbell, CA. 1-408-345-4880, fax 1-408-345-4884, www.precedence.com.

Programmable-logic heavyweights pack a punch

Altera and Xilinx, the 800-lb gorillas of the programmable-logic business, are once again targeting each other with new-process and -product announcements. Altera is now sampling a faster "-2'' speed grade for its Flex 10K product line, and the company estimates performance improvements of 22 to 40%. Altera also announced its upcoming 2.5V Flex 10KB chips, based on a five-layer-metal, 0.25-µm drawn process and aiming at greater than 66-MHz system performance. Altera plans to offer the 100,000-gate EPF10K100B for sampling in the second quarter of next year, and devices with 30,000 to 250,000 typical gate densities, including embedded SRAM, will become available through the remainder of 1998.

Altera also hopes to ship its first Raphael devices with an estimated 500,000-gate count in 1999. Raphael will build on the Flex 10K routing structure and include look-up-table, product-term, and RAM cores in each logic block. Targeting 80- to 100-MHz system performance, Raphael will also include a second-generation PLL. Altera plans even higher Raphael-family gate counts with the next-generation 0.18-µm process.

Unlike Altera and Lucent Technologies (Allentown, PA), which announced their 0.25-µm processes in August, Xilinx's first 0.25-µm-based chip, the XC40125XV, is already available for sampling. Additional XC-4000XV family members having 125,000 to 250,000 typical gates will become available for sampling next year. XC4000XV devices, which target 100-MHz internal and 80-MHz I/O performance, are architecturally backward-compatible with 3.3V XC2500XL chips and offer compatible footprints (except for core-voltage differences) and packages. The XC40125XV-2 costs $1500 (100) in a BGA package, but a HardWire cost reduction ranges from $60 to $100, depending on volume. (For more on HardWire, see "Moving beyond programmable logic: if, when, how?")

Xilinx also has next-generation architecture plans in the Virtex family. Notable enhancements include highly flexible I/O buffers; multiple PLLs; and dedicated 4-kbit, dual-ported SRAM blocks. Previously, Xilinx relied exclusively on the distributed RAM inside each logic cell's look-up table to synthesize embedded memory. The first Virtex device is due to become available for sampling in mid-1998 and aims for greater than 100-MHz internal and I/O performance. It will contain 6000 logic cells, 260 I/O pins, and 8 kbytes (16 blocks) of dedicated RAM, and it will sell for less than $400 (100). Xilinx predicts that, by the end of next year, it will offer a family of devices having 1500 to 25,000 logic cells, 190 to 700 I/O pins, eight to 30 SRAM blocks, and 100,000 to 1 million system gates, including embedded SRAM.

--by Brian Dipert

Altera Corp, San Jose, CA. 1-408-894-7000, fax 1-408-435-1394, www.altera.com.

Xilinx Inc, San Jose, CA. 1-408-559-7778, fax 1-408-879-4780, www.xilinx.com.

Transceiver front end uses
active mixer to eliminate IF stage

ICs for 900 MHz are showing how far analog-IC vendors have come in putting RF/IF systems on a chip (see "Radio IC provides mixed-signal half of 900-MHz cordless phone," EDN, Oct 9, 1997, pg 20). Maxim's Max2420 comes in a 28-pin SSOP and uses an architecture that reduces the number of filters and stages needed for cordless phones, wireless modem links, and similar transceivers. The device includes an on-chip local oscillator that needs only a varactor-tuned LC tank.

The receiver-signal path uses a 10.7-MHz IF without complex filters, which eliminates the need for a second downconversion stage. An adjustable-gain low-noise amplifier and an image-rejection downconverter with typical 35-dB suppression produce a combined 4-dB received-noise figure and a 2-dBm-input third-order intercept point (IIP₃). The transmitter comprises a variable-gain IF amplifier with greater than 35 dB of control range and an image-rejection upconverter with 35 dB of rejection. You can directly upconvert a digitally synthesized signal, thus eliminating trims and other stages. In addition, the power amplifier produces a 2-dBm output, which you can use directly or as a driver to another power-amplifier stage.

The Max2420 also includes a 64/65 dual-modulus prescaler, which you can use with an external PLL or as a buffer in a synthesizer. Typical current consumption for the 2.7 to 4.8V IC is 23 mA for the receiver stage, 26 mA for the transmitter stage, and 9.5 mA for the internal oscillator. Shutdown-mode current is 0.5 µA.

--by Bill Schweber

Maxim Integrated Products, Sunnyvale, CA. 1-408-737-7600, fax 1-408-737-7194, www.maxim-ic.com.

Datapath compiler supplements logic synthesis

If you employ Synopsys' Design Compiler for logic synthesis and usually design datapaths on your chips, you may want to check out the company's Module Compiler. You use this new synthesis tool for designing datapath functions by synthesizing gate-level descriptions from high-level structural descriptions. This design flow is similar to synthesizing gate-level logic from RTL Verilog or VHDL. Module Compiler takes a description written in a parameterized Verilog-like language and quickly compiles an optimized-gate representation of the datapath. Synopsys claims that the tool can synthesize a 20,000-gate design in 2 minutes and optimize the design in 8 more minutes.

Module Compiler uses the same technology libraries as Design Compiler, giving you a choice of more than 300 libraries from more than 70 vendors. You work with both tools on most designs, synthesizing the control logic with Design Compiler and datapath blocks with Module Compiler. (Design Compiler does not efficiently synthesize datapath blocks.) For your datapath designs, Module Compiler comes with a rich set of predefined functions for implementing basic-logic and more advanced functions, such as multiplexers/demultiplexers, decoders, shifters, accumulators, RAMs, ROMs, FIFOs, ALUs, and registers. The tool also supports complex-datapath-design techniques with features such as automatic pipelining; automatic latency management; arithmetic-operator merging; and multiple architectures for add, multiply, and compare operations.

Module Compiler costs $150,000. Synopsys is developing floating-point-library functions, which will be available later at additional cost.

--by Jim Lipman

Synopsys, Mountain View CA. 1-650-962-5000, fax 1-650-965-8637, www.synopsys.com.

ColdFire heats up

Motorola's ColdFire, or variable-length-RISC, architecture is about to evolve as the company releases the Version 3 (V3) core. Similar to the Version 2 (V2) core, V3 comprises two decoupled subpipelines: an instruction-fetch pipeline (IFP) and an operand-execution pipeline (OEP). An instruction buffer separates the two pipelines and minimizes pipeline stalls. Motorola's design goals for V2 included making the core as small as possible. Hence, V2's IFP is a simple two-stage pipeline: instruction-address generation and instruction fetch.

Motorola's design goal for V3 was to stretch the pipeline to allow the device to operate at clock frequencies of 90 MHz and higher. V3's IFP includes two additional stages to help pipeline the address-generation and instruction-fetch phases. One of the additional stages is an early instruction decode to help reduce the decoding time. This concept, which Motorola borrowed from the 68060, includes some branch-acceleration techniques. For example, the early-decode mechanism considers that backward branches are taken. By default, the mechanism considers forward branches taken, but a condition-code register bit allows you to set up forward branches to be not taken.

In the V2 implementation, the instruction buffer comprises a three-long-word-entry FIFO buffer. The V3 implementation holds three complete instructions, regardless of length. This instruction buffer essentially converts variable-length into fixed-length instructions.

Both V2 and V3 cores have the local, high-speed, tightly coupled KBus. On V2 implementations, this bus lets the core perform a 32-bit fetch from internal memory in a single clock cycle but limits operating frequency. V3 uses a two-stage, pipelined KBus that adds one cycle to most operand-read accesses; however, the increased operating frequency offsets the extra cycle. The extra clock has no effect on operand writes because the KBus-to-MBus controller buffers the write.

Other new features of V3 include multiple clock domains that allow the core to operate at a higher frequency than the remainder of the µP. V3 also includes an optional hardware divider and a multiply-accumulate unit; you can also use these new units on V2 implementations. The V3 core is available now for synthesis into your designs, and the first standard products will become available next year.

--by Markus Levy

Motorola, Phoenix, AZ. 1-800-441-2447, www.mot.com.

Algorithm in silicon smoothes
color, "jaggies" in flat-panel displays

The virtues of passive-matrix, super-twisted-nematic (STN) LCDs for flat-panel displays are their reasonably good image quality and low cost (although more expensive active-matrix thin-film transistors (TFT) displays have better image quality). However, you can turn the STN pixels only fully on or off, so to present true color shading and line smoothness, you must use time- or space-domain-based dithering techniques. These, in turn, can cause perceived image problems, such as "flicker" or "swim," and limit the number of colors that you can represent.

To address these concerns, the ADE100 dedicated display-engine IC from Arithmos resides within the LCD panel and incorporates a proprietary enhanced-gray-scale-control algorithm that strives to eliminate image artifacts and provide true-color shading of 16.7 million colors. It converts the 24-bit, TFT-compatible digital video stream from the graphics-controller interface--either standard analog or newer low-voltage differential-signaling digital--into an STN data stream for the flat panel. Arithmos based the algorithm in the ADE100 both on a model of the optical response of STN liquid-crystal material and on a model of the visual response of humans. The algorithm adaptively modulates and controls the relative phase of localized groups of pixels.

Using the ADE100, you can achieve SVGA, XGA, and SXGA resolution with single or dual pixels per clock cycle with refresh rates of 120 to 240 Hz, depending on the response time of the flat panel. An internal, preprogrammed timing controller supports many standard STN panels, and on-chip PLLs generate memory and output clocks. The $25 (1000) IC requires a 256k×32-bit synchronous graphics RAM for most operating modes, and two SGRAMs for SXGA with four-times acceleration.

--by Bill Schweber

Arithmos Inc, Santa Clara, CA. 1-408-982-4490, fax 408-982-4481, www.arithmos.com.

Rugged position sensor is bulletproof

Model 657 Super Cube position sensor from Spectrol is virtually immune to damage and thrives in harsh environments. The 5/8-in. sensor is available with standard resistance values from 50 ohms to 25 kilo-ohms, power ratings as high as 0.5W at 40°C, and a ­40 to +125°C operating-temperature range. The device accommodates as many as 1 million shaft revolutions. Options include special shafts and bushings, mechanical stops, custom wire harnesses in lieu of terminals, and extended-temperature ranges.

The 657 uses a conductive-plastic screening process and laser trimming to provide a 2%-accurate output signal. The rugged thermoplastic case uses back filling and an epoxy seal to provide environmental protection. The sensor withstands shock as high as 30g and 15g vibration at 10 to 2000 Hz. The price is less than $6 (production quantities).

--by Bill Travis

Spectrol Electronics Corp, Ontario, CA. 1-800-624-8902, fax 1-909-923-6765, www.spectrol.com.

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