| Figure
1 |
 |
| For designs
having as many as several tens of thousands of
gates, high-pin-count programmable-logic devices
and ASICs have equivalent bond-pad-driven die
sizes and comparable costs (courtesy QuickLogic).
|
| Figure 2 |
 |
| The percentage of
total ASIC conversion work you do depends on
which conversion option and vendor you select
(courtesy Orbit). |
| Figure 3 |
 |
| Scan-test
circuits for automatic test-program generation
(ATPG) improve overall ASIC test coverage and
reduce the vector-set size for sequential logic. |
| Figure 4 |
 |
| HardWire maps the
FPGA's logic blocks and routing resources onto
equivalent gate-array die locations (courtesy
Xilinx). |
| Figure A |
 |
| Routing and logic
propagation-delay differences between
programmable-logic devices and ASICs may cause
functional errors during conversions (courtesy
Lucent Technologies). |
| Back |
