| Figure
1 |
10 mV/DIV
(AC
COUPLED) |
 |
20 mV/DIV
(AC
COUPLED) |
 |
| (a) |
1 µSEC/DIV |
(b) |
50 µSEC/DIV |
|
| The typical
switching regulator's output (a) has wideband
spikes that are difficult to suppress. Adding a
linear regulator can eliminate ripple, but the
wideband spikes remain (b). |
| Figure 2 |
 |
|
A (10V/DIV) |
 |
| |
B (1A/DIV) |
| |
C (10V/DIV) |
| |
D (1A/DIV) |
| |
E (100 µV/DIV) |
| |
|
20 µSEC/DIV |
| (a) |
(b) |
| TRACE |
DESCRIPTION |
| A |
SWITCHING-TRANSISTOR
COLLECTOR VOLTAGE |
| B |
SWITCHING-TRANSISTOR
CURRENT |
| C |
SWITCHING-TRANSISTOR
COLLECTOR VOLTAGE |
| D |
SWITCHING-TRANSISTOR
CURRENT |
| E |
CURRENT
OUTPUT NOISE |
|
|
| Based on the
performance of IC1, a 5-to-12V
converter (a) has only 100 µV of output noise
(b, Trace E). |
| Figure 3 |
| 5 mV/DIV |
 |
10 mV/DIV
(AC COUPLED
ON 200-mA
DC LEVEL) |
 |
| (a) |
10 µSEC/DIV |
(b) |
10 µSEC/DIV |
|
| Ripple at the
first LC output has no wideband spikes (a). The
input current (b) contains small sinusoidal
variations, which the input supply can easily
absorb. |
| Figure 4 |
| LSB |
1.5 |
 |
LSB |
1.5 |
 |
| 1.00 |
1.00 |
| 0.50 |
0.50 |
| 0.00 |
0.00 |
| -0.50 |
-0.50 |
| -1.00 |
-1.00 |
| |
|
128 |
16512 |
32896 |
49280 |
|
|
128 |
16512 |
32896 |
49280 |
| (a) |
|
CODE
|
(b) |
|
CODE
|
| LSB |
1.5 |
 |
LSB |
1.5 |
 |
| 1.00 |
1.00 |
| 0.50 |
0.50 |
| 0.00 |
0.00 |
| -0.50 |
-0.50 |
| -1.00 |
-1.00 |
| |
|
128 |
16512 |
32896 |
49280 |
|
|
128 |
16512 |
32896 |
49280 |
| (c) |
|
CODE
|
(d) |
|
CODE
|
|
| Crossplots of a
16-bit A/D converter's differential (a, b) and
integral (c, d) linearity show virtually
imperceptible differences between performance
with a bench supply (a, c) and the LT1533-based
supply circuit (b, d), respectively. |
| Figure 5 |
A (5V/DIV)
B (100 µV/DIV) |
 |
A (5V/DIV)
B (100 µV/DIV) |
 |
| (a) |
500 nSEC/DIV |
(b) |
500 nSEC/DIV |
A (5V/DIV)
B (100 µV/DIV) |
 |
A (5V/DIV)
B (100 µV/DIV) |
 |
| (c) |
500 nSEC/DIV |
(d) |
500 nSEC/DIV |
|
| The relationship
between power-switch slew rate (Trace A) and
output noise (Trace B) is clear. The highest slew
rate (a) causes the most noise. Slower rates (b,
c) decrease noise until you reach the slew rate
that corresponds to the lowest noise performance
(d). |
| Figure 6 |
 |
| Noise, slew time,
and efficiency are interrelated. Increasing the
slew time decreases the noise with a 6% penalty
in efficiency up to a point; increasing the slew
time beyond 1.3 µsec reduces efficiency without
further reducing noise. |
| Figure
7 |
 |
| Grounding the
duty pin and biasing the FB pin puts the
regulator into a 50%-duty-cycle mode. The circuit
then produces a floating, unregulated output in
proportion to T1's center-tap voltage.
|
| Figure 8 |
 |
| A hysteretic
burst-mode loop lowers quiescent current to 100
µA and maintains output noise of 100 µV. |
| Figure 9 |
 |
| A cascode stage
comprising Q1, Q2, and
related RC components can withstand 100V
transformer swings from 20 to 50V inputs and
permits the circuit to control a 5V, 2A output. |
| Figure 10 |
 |
| Optoisolator
feedback to the switching regulator's VC
pin closes the loop to produce a fully floating,
regulated output with a 7500V peak-breakdown
capability. |
| Figure A |
 |
| The proper test
setup is critical to making accurate low-noise
measurements. The instruments you choose must
have sufficient bandwidth to capture
high-frequency noise spikes. |
| Figure B |
| 100 µV/DIV |
 |
| 2 nSEC/DIV |
|
| Applying a
subnanosecond rise-time step to the test setup
confirms a rise time of 3.5 nsec, or bandwidth of
100 MHz. |
| Figure C |
| 100 µV/DIV |
 |
| 20 nSEC/DIV |
|
| With no input and
the regulator off, the noise floor of the test
setup is less than 100 µV. |
| Figure D |
| 100 µV/DIV |
 |
| 10 nSEC/DIV |
|
| With confidence
in the test setup, you can measure the output
noise of the circuit as approximately 100 µV. |
| Back |
