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December
18, 1997
Receiver now available
EDN published a Design Idea of mine in
the Sept 25, 1997 issue ("Single chip builds tiny
aircraft receiver," pg 170). The aircraft radio receiver has been
well-received (no pun intended) by several readers. So much so that Fred Reimers, who runs
FAR Circuits, has agreed to make a pc board available for the project.
You can reach Fred at www.cl.ais.net/farcir/. He charges $4.50
plus $1.50 shipping and handling per order for a nicely done, single-sided pc board.
Also, one part value was omitted from Figure 1.
The zener diode is a 1N748A, 3.9V.
Steve Hageman, Hewlett-Packard Co, Santa Rosa, CA
Corrections and updates
The Design Idea "Program converts
temperature from RTD sensor" (EDN, June 5, 1997, pg 116) features
a C program to convert platinum RTD resistance into temperature. It is incorrect. You
should calculate RTD temperatures using the Callendar-Van Dusen equation. Over a limited
temperature range, such as 0 to 100°C, you can use a linear approximation. In either
case, the coefficients depend on the purity of the platinum used in the sensing element.
National Instruments' Application Note 046 (available on www.natinst.com)
is a tutorial on measuring temperature with RTDs. Also see Handbook of Transducers
by Harry Norton, Prentice Hall, 1989.
Debora Grosse, EDN
Contributing Editor
In the Design Idea "Simple regulator
monitors its input voltage" (EDN, Sept 12, 1997, pg 110), the
label for the IC is missing. The IC is a MAX8866.
In "Point-to-point
ring turbocharges PCI bus" (EDN, Nov 6, 1997, pg 13), the
144-nsec-latency value should have been called the ring-transport delay. This delay is the
average round-trip delay that would occur for the ring portion of a transaction on a
16-node Sebring Ring. The total latency that a PCI master sees is the transport delay plus
the delays through the SRC (Sebring Ring Controller) chips at both the initiator and the
target nodes and any wait states on the target bus. These delays are roughly comparable
with the delays through a PCI-to-PCI bridge chip.
An SRC chip does not have to wait more than 56
nsec to begin transmission on the ring, whereas one may have to wait for more than one
full PCI burst to complete before receiving a bus grant in a conventional PCI environment.
The net result is an average latency on the order of 500 nsec for a single word read, even
when multiple gigabytes/sec of data are being pushed through the network.
Jack Regula, Sebring Systems, Los Gatos, CA
In "Advanced DRAM puts you in
the fast lane" (EDN, Oct 9, 1997, pg 52), Table 5 was incorrect. Thanks to Jerzy R Chrzaszcz,
PhD, from the Computer Graphics Laboratory at the Institute of Computer Science, Warsaw
University of Technology, Poland, for his assistance in correcting this information. The
corrected table appears below.
Sound off
Send your letters to Signals and Noise Editor,
EDN, 275 Washington St, Newton, MA 02158, or e-mail us at bmorrison@edn.cahners.com. Our fax is
1-617-558-4470.
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