January 15, 1998

Transfer data frames over asynchronous RS-232C lines

SK Shenoy, Naval Physical and Oceanographic Lab, Kochi, India

The asynchronous RS-232C interface is a simple, low-cost option for interconnecting processor-based systems. In many applications, you need to transfer variable-size messages. However, the character-oriented RS-232C protocol offers no direct mechanism for transferring messages as self-contained packets. The method described here uses an obscure feature found in most UART devices to indicate packet boundaries. The feature is the capability to transmit and recognize the "Break" character. This character is nothing but a "space," or low, in the transmit line of a duration equal to or greater than an entire asynchronous character-transmission time, including the start and stop bits (Figure 1). In this framing method, the message data bytes sandwich between two Break characters to form a data frame (Figure 2).

A Turbo C program demonstrates the transfer of variable-size messages between two PCs with 8250-compatible UARTs (Listing 1). To download the program,  click here DI-SIG, #2140.

A null-modem cable interconnects the PCs' COM ports. The same routine works with most other UARTs. The method allows data-packet reception in interrupt mode and wastes no CPU overhead looking at each character to detect packet boundaries. Instead, the UART does the detecting. Because the Break is not a legitimate data character, it is data-transparent, and you can use it for binary-data exchange. You can use this "in-band" scheme with repeaters and modems, as long as they permit transmission of the Break condition. The packet-boundary detection is relatively immune to a missed Break character and to data errors. You can render the detection more robust by introducing data-length and check-sum fields in the frame to allow detection of errors and flow control using an RTS/CTS (request-to-send/clear-to-send) handshake.

To transmit a Break, set bit 6 (Set Break) of the line-control register to 1. The UART then sets its Tx line low, until bit 6 encounters a 0. Transmission of a Null character (00 hex) makes the duration of the Break equal to one character-transmission delay. Bit 6 of the line-status register (Tx Machine Status) indicates when this delay is over; then, the Break bit resets. To enable detection of the Break, bit 2 of the interrupt-enable register (interrupt-on-Rx-error condition) sets during UART initialization. Bit 0, set to 1, enables receive-data interrupts. In the interrupt-service routine (ISR), bits 1 and 2 of the interrupt-identification register indicate the interrupt type.

A global variable, Receive_Count, initialized to zero, handles frame reception. Upon detection of a Break, the UART raises an interrupt. If Receive_Count is zero, the interrupt is a start-of-frame break and the UART ignores it. (You can use the interrupt to set a Packet_Receive_On flag.) On each subsequent receive interrupt, the ISR stores the data in the Receive buffer with Receive_Count as the index. If Receive_Count is nonzero when the Break interrupt is raised, the interrupt is an end-of-frame break. Then the routine calls the frame-processing function and resets Receive_Count to zero. (DI #2140)

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