February 2, 1998

SIGNAL INTEGRITY: To tee or not to tee

Howard Johnson, PhD

When you try something tricky--even if you sit with the layout person during design to make it work--the design will ultimately self-destruct when someone else revises the layout as part of a future product upgrade.

You cannot satisfactorily terminate the net topology in Figure 1. What I mean is, you can't obtain a crisp first incident wave that is full-size without reflections and still meet the demands of good circuit-design practice. You can satisfy any combination of some, but not all, of the above requirements. (If you are interested, details about the waveforms and simulation parameters described in this article are available at www.sigcon.com/articles/edn/tee.htm.)

With a fast, 1-nsec driver, the basic problem with this topology is that the signal delay on each branch (1 nsec) is longer than the rise time. Such a net, if left unterminated, displays what you would expect: full transmission-line characteristics with lots of overshoot and ringing (Waveform 1).

A slower driver improves the ratio of line delay to rise time. For example, a 15-nsec driver is slow enough to damp out the ringing and reflections, but, unfortunately, such a slow driver gives you a long, sloppy, rise time. You lose the first criterion: a nice, crisp first incident wave (Waveform 2).

Attenuation can help. A combination of a 50V series termination at A and 50V end terminations at C and D damps all reflection modes. Unfortunately, this approach shrinks the received signal to only one-third of normal size--too small for practical use (Waveform 3).

Partial terminations can help calm, but not totally cure, the ringing behavior. With 100V terminations at C and D, the first incident wave looks perfect. But, after a while, the reflections trapped between the low-impedance driver at A and the mismatch at junction B cause the received signal to overshoot, crest, and rattle about (Waveform 4).

If you are willing to use a sneaky trick, you can have it all. The trick is to implement segment A-B as a 50V line while implementing segments B-C and B-D as 100V lines. (It takes really skinny microstrips to get this approach to work, but it's possible.) When the signal from A hits Junction B, it sees two 100V loads in parallel, which is a good match for the 50V segment A-B. No reflections result. Two 100V end terminations, one at C and another at D, perfectly terminate the whole net. The signals look perfect (Waveform 5).

Is this approach good practice? It depends on your company's internal design procedures. Most companies do not have a good way to document, track, and enforce tricky high-speed-design rules. For example, if you write a little thesis on your schematic about some high-speed-design trick you've used, it's unlikely that the layout person will ever see it. It's not his job to read your schematic. His job is to hook up your netlist using the part footprints you supply and using standard design rules. When you try something tricky--even if you sit with the layout person during design to make it work--the design will ultimately self-destruct when someone else revises the layout as part of a future product upgrade. The tee is too tricky to survive long-term.

If you throw the tee overboard, the situation improves. For example, if you split Driver A into a pair of low-skew drivers and then use an independent, point-to-point, source-terminated link from each driver to each load, the tricky constraints disappear. You've used a standard design practice. The dual-driver topology works now and will work in the future, when some kid who doesn't know an ohm from a hole in the ground picks up your design and tries to figure out what you did.

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