February 2, 1998

WHAT'S HOT IN THE DESIGN COMMUNITY

25-year-old Z8 gets an overhaul

Aside from process-technology changes, Zilog's Z8 mP has remained unchanged since the company introduced the architecture in 1973. This year, Zilog is offering microcontrollers with the Z8Plus, a new beefed-up core. Although this core is software-compatible with the traditional Z8, Zilog expects the Z8Plus to   outrun the Z8 by as much 50%. This perform-ance improvement results primarily from a reduced system clock and a fixed instruction-cycle time. All instructions on the Z8Plus execute in five system clocks; the minimum instruction cycle time for the Z8 is six system clocks, and some instructions require as many as 20 clocks. The fixed-length instruction time not only yields higher performance, but also helps you write more deterministic software.

Interrupt latency on the Z8Plus is also shorter than that of the Z8. The interrupt process is two instructions plus completion of whichever instruction may have started--a total of 15 system clocks in the worst case and 10 clocks in the best case. On the other hand, the Z8 requires 24 clocks plus as many as 20 clocks for the longest instruction in progress plus two for setup, for a worst-case total of 46 system clocks. Furthermore, the Z8's interrupt-return instruction takes 16 clocks, compared with only five on the Z8Plus.

Another advantage of the Z8Plus is its lower power consumption, which results from having fewer clocks per instruction than the previous design, as well as other design improvements. Although the family's devices differ from each other in peripherals and memory, Zilog specifies the first Z8Plus part at 6 mA (5.5V and 10 MHz). Compare this with 20 mA for the similarly featured Z86E04 running at 5.5V and 12 MHz.

Zilog also added code-rollover protection to the Z8Plus, although many designers will continue to use the device's watchdog timer. An advantage of rollover protection is its instant response to program error; compare this response to the several milliseconds that a watchdog timer may take to time out. On the Z8, address 00h is the first interrupt vector, and it has no instruction associated with it. With the Z8Plus, you can specify a short jump and an address at location 00h.

Zilog redesigned the Z8Plus' bus to help reduce noise. It's difficult to perform a quantitative comparison of noise generation between the Z8Plus and the Z8 because most chip noise comes from the oscillator and I/O switching. However, some of the Z8Plus' noise reduction is because of its nonprecharged bus. Additionally, some noise improvement results from the device's ability to use a slower crystal.

The Z8E520 is Zilog's first product to contain the Z8Plus core. This device includes USB logic and targets USB, PS/2, and serial-mouse designs. It contains 6 kbytes of ROM and fits into a 20-pin DIP, SOIC, or SSOP. It sells for $2.50 (5000).

This year, Zilog plans to offer the Z8E001 containing a 1-kbyte one-time-programmable ROM, a 64-byte register file, three timers, and an analog comparator. It will operate from dc to 10 MHz at 3 to 5.5V. The E001 comes in 18-pin DIPs, SOICs, SDIPs, and SSOPs and sells for $0.74 (10,000). Zilog will also offer the Z8E00100ZEM emulator for $450, and a $100 version will also be available. This emulator includes real-time trace capability with source-level debugging and performs EPROM programming.

Zilog, Campbell, CA. 1-408-370-8000, www.zilog.com.

AGP-enabled graphics IC slashes 3-D subsystem costs

A new member of ATI's Rage family of ICs--the $20 (10,000) Rage IIC--targets cost-sensitive systems yet still of-fers AGP support, 2- and 3-D graphics acceleration, a video scaler, and a 200-MHz DAC. The IC employs a footprint that's compatible with the high-end 3-D Rage Pro IC that includes hardware support for 3-D-triangle setup, allowing PC OEMs to produce a single motherboard yet equip it for different target markets. The new IC includes full PCI power-management support and supports the ATI media channel for connection to video sources, such as tuners and cameras. Proving the value the Rage IIC offers for the price, ATI also announced the Xpert XL add-in board that sells at retail for $99 for PCI or AGP versions with 4 Mbytes of extended-data-out DRAM.

ATI Technologies Inc, Thornhill, ON, Canada. 1-905-882-2600, www.atitech.com.

Graphical programming tool offers multithreading and more

Version 5.0 of National Instruments' (NI's) LabView graphical interface package for developing real-time-applications is more powerful and easier to use than previous versions. Topping the list of improvements is multithreading, which, the company claims, was previously available only to users of text-based programming languages. Multithreading improves program reliability and execution speed, especially on computers with multiple CPUs. Developers who use LabView need not learn any new programming practices. Recompiling applications that programmers developed in earlier versions produces multithreaded applications. However, advanced programmers can use a simple dialogue box to control threads. A related enhancement in V5.0 allows distributed computing, wherein different portions of a program execute on different machines on a network.

LabView V5.0 is now an ActiveX container. Thus, developers who use LabView can now use 32-bit custom controls and ActiveX documents, just as users of Visual Basic and Visual C++ can. To reuse such a code module, you need only drop it onto a LabView front panel. Moreover, once such a module is part of a LabView application, you have several choices for editing the module's  properties.

Two features aim at making programmers' lives easier. One feature that users requested and NI's programmers, until now, resisted including, is the ability to undo changes. NI calls the other feature "graphical differencing." When it comes to figuring out how two versions of a program differ from each other, developers who use traditional text-based languages have had an advantage over graphical programmers. Text editors can easily find differences among source files. LabView 5.0 adds a facility that lets you see how versions of a graphical program differ from each other.

LabView's prices remain un-changed. For PCs running Windows NT, 95, or 3.1, LabView costs $995; for Mac OS, $1995; for Sun and HP workstations, $2995; and for Concurrent PowerMax, $4995. Upgrades from earlier versions cost $295 for Windows and Mac operating systems and $395 for Unix.

National Instruments, Austin, TX. 1-800-258-7022, fax 1-512-794-8411, info@natinst.com, www.natinst.com.

New verification tool has a formal air

Synopsys, best known for its logic-synthesis tools, has added a gate-level verification tool, the Formality formal equivalence checker. You use an equivalence checker to exhaustively verify whether two representations of the same design are logically equivalent. An advantage of formal-verification tools over traditional event-driven or cycle-based simulation tools is that formal verification, like static-timing analysis,   requires no vectors.

Formality first checks whether a synthesized, gate-level design is equivalent to the presynthesis RTL representation of the design. You then reuse the tool after any design operation that adds or deletes logic functionality, such as adding scan-testability circuitry or modifying a clock tree. Unlike some other equivalence checkers based on a single equivalence solver, Formality has many solvers. During design analysis, the tool applies the solver best suited for a design structure. This feature increases total verification speed, which is orders of magnitude faster than gate-level, vector-based simulation. A hierarchy-management feature in the tool lets you compare designs that may be logically equivalent but have mismatched design hierarchies.

A gate-level schematic debugger helps you isolate mismatches that Formality finds. The tool highlights problems on the schematic but does not automatically go from the schematic to the problem code in the HDL file. Also, when you find an error between circuit representations, Formality cannot tell you how to correct the problem; that redesign step is up to you.

Formality uses Verilog, VHDL, or EDIF data. The tool is tightly coupled with Synopsys' Design Compiler logic-synthesis tool. This coupling lets you use Formality with more than 350 ASIC-synthesis libraries that support Synopsys tools. On the other hand, if you use a tool other than Design Compiler for logic synthesis, you probably do not want to use Formality for equivalence checking. Formality, running on Unix-based workstations, costs $100,000. (For additional information on formal-verification tools, see "Chip verification: a formal affair?" EDN, Jan 1, 1998, pg 85.)

Synopsys, Mountain View, CA. 1-650-962-5000, fax 1-650- 965-8637, www.synopsys.com.

Precision PCI reset generator hits triple play

Any power-supply monitor for PCI designs has to be both fast and accurate while babysitting three supplies. The LTC1536 from Linear Technology puts 5 and 3.3V voltage monitors and a third adjustable monitor into an eight-pin MSOP device with threshold accuracy of 0.75%. The IC generates a reset signal within less than 500 nsec if any power rail falls more than 500 mV below specification and within 100 nsec if the 5V rail drops below the 3.3V rail by more than 300 mV. Drawing just 100 mA typical supply current, the LTC1536 provides reset operation for the 5 and 3V rails to as low as 1V.

You can also manually initiate a reset via a pushbutton input. By pushing the button for less than 2 sec, you cause the IC to generate a 100-msec "soft" reset, which is useful for designs that must detect the presence of transients and reset the CPU while not affecting DRAM; holding it down for more than 2 sec causes the device to produce, on a separate IC output pin, a 200-msec "hard" reset signal that is equivalent to a power-fail/power-on reset.  The LTC1536 costs $2.65 (1000); a similar device, the LT1326, costs $2.20 (1000), and targets non-PCI applications but requires just a 20-mA supply current.

Linear Technology Corp, Milpitas, CA. 1-408-432-1900, fax 1-408-434-6441, www.linear-tech.com.

Vantis opens the gate to FPGAs

Vantis, the programmable-logic subsidiary of AMD (Sunnyvale, CA), enters the market for high-gate-count FPGAs with the SRAM-based VF1 family. VF1 devices have 12,000 to 36,000 logic gates. Additionally, the devices integrate 3584 to 6144 bits of high-speed RAM, which the company does not include in its logic-gate counting. Vantis optimized the RAM and associated dedicated logic for dual-port configurations (one read and one read/write) and divided it into 128-bit (3234-bit) blocks.

VF1's variable-grain architecture is conceptually reminiscent of the flexible granularity of QuickLogic's (Sunnyvale, CA) pASIC2 and pASIC3 antifuse FPGAs. The lowest level building block, a microcombinatorial element, or mCE, comprises a three-input look-up table and decoding logic. Two mCEs plus a multiplexer form a configurable combinatorial element (CCE). Add a configurable sequential element (CSE) (essentially, a D flip-flop plus decoding logic), and you get a configurable building block (CBB).

Up one level in the hierarchy is the variable-grain block (VGB), comprising four CBBs plus carry, wide gating, and control logic. Each VGB can implement one function with as many as 16 inputs, two functions with as many as eight inputs, or four functions with as many as four inputs. Four VGBs combine to form a "Super VGB," which can if necessary implement one 32-input function. Vantis adapted its 0.25-mm, four-layer-metal process from AMD's K6 mP. This process provides an abundance of variable-length inter- and intra-VGB interconnect resources to help you wire everything together. Four dedicated clock networks span the chip, and the I/O buffers include separate input and output registers and several user-programmable options. Vantis even includes on-chip 200-MHz PLLs in two corners of the die.

Robust EDA support is essential to insulating VF1 architectural complexity from end users and enable them to exploit its capabilities. Vantis reports that it has worked closely with third-party schematic-entry, synthesis, and simulation vendors. At product introduction, the company also hopes to ship beta front-end device libraries, back-end map, and place-and-route software as well as 66-MHz PCI initiator and target firm cores. The company plans production-software support and sampling of the 25,000-gate VF1025 for the end of the second quarter of this year. The $46 VF1012 commercial-temperature version comes in a 144-pin TQFP. The VF1020 and VF1036 will follow in the third quarter.

Vantis Corp, Sunnyvale, CA. 1-408-732-0055, fax 1-408-774-8461, www.vantis.com.

Unusual technology yields 500-MHz-bandwidth analog storage scope

Analog-scope technology is alive and well, and it still yields impressive products at competitive prices. To prove it, Iwatsu has announced the TS-8500, a $12,495, four-channel (two channels with full attenuators), 10-trace unit, with 500-MHz bandwidth and a writing rate of 5 div/nsec.

The specs alone say that this is not your father's analog scope, but the fact that the scope uses unusual technology unavailable in your father's day is not immediately obvious. Unlike virtually all other scopes, analog and digital, the screen is not the CRT. The scope uses a 2-in.-diameter scan-converting storage tube inside to drive the 5.5-in.-diagonal LCD on which you view waveforms. According to Iwatsu, the result is the highest brightness level ever in analog scopes.

Two channels provide 2-mV/div sensitivity and both 50V and 1-MV inputs. The other two channels provide 100 and 500 mV/div and 1-MV sensitivity. Display modes include normal, X-Y, and expanded-sweep. The scope has dual timebases and provides full delayed-sweep operation. As with many analog scopes, you can add channels 1 and 2 (those with high sensitivity and full attenuators), and you can invert Channel 1. The combination of inverting and adding creates, within limits, a differential input.

Iwatsu America Inc, Carlstadt, NJ. 1-201-935-8486, fax 201-935-8533, iwatsu@access.digex.net, www.iwatsu.com.

Add wizardry to your core-based programmable-logic designs

Max+Plus II, Altera's programmable-logic-design tool suite, now includes the MegaWizard shell for developing customized logic cores. You use MegaWizard to optimize a parameterized function, described in an HDL, for a specific application without modifying HDL code.

For every core in MegaWizard, the core developer (either Altera or a third-party vendor) has written a program defining the graphical user interface (GUI) you use to parameterize the core. The GUI is platform- and tool-independent and lets you display a schematic symbol for the function and a list of parameters you can set. When you compile the core in MegaWizard, the synthesis engine in Max+Plus II creates the required core functionality with your parameter values.

You can use MegaWizard on library-of-parameterized-module (LPM) functions, including arithmetic operations, counters, and multiplexers. Working with its core partners in the Altera Megafunction Partners Program, Altera will develop future MegaWizard shells, including FFT, PCI, and DSP functions for cores in the MegaCore library. Prices for Max+Plus II with  MegaWizard are $995 to $4995, depending on features and capability.

Altera, San Jose, CA. 1-408-544-7000, fax 1-408-544- 6410, www.altera.com.

µC family expands performance and memory range

Microchip's PICmicros, based on a Harvard architecture, make it easy to add instruction bits because the program and data memory are different sizes. The new PIC16C1XX family, which outperforms the company's high-end PIC17CXX family, has 16 address bits and a linear address space for as much as 4 Mbytes of program memory and 4 kbytes of data memory. Using a 16-bit instruction width, the PIC supports 68 instructions (an increase from the 56 on the PIC17CXX), including a single-cycle 838-bit multiply. In addition, the device has 65 single-word instructions. Despite the change in instruction width, the PIC16C1XX is source-code-compatible with the PIC16CXX. The new architecture also supports three 12-bit data pointers with five addressing modes.

Using a 10-MHz external crystal, the PIC16C1XX has a 100-nsec instruction cycle. An internal four-phase clock multiplier allows peripherals to run at 40 MHz. The PIC16C1XX has a 32-word-deep hardware stack, an increase from eight and 16 deep on other family members. The PIC16C1XX also includes a software stack to better support high-level languages, such as C. Microchip claims that its new architecture is about 30% better than its previous architecture for handling C code. The company also improved the PIC's interrupt capability by adding a fast interrupt mode for external or internal interrupts. The fast interrupt performs hardware-context saving using shadow registers. A bit in the return-instruction operation code tells the CPU whether to return from an interrupt using the shadow or the regular stack.

With the PIC16C1XX, Microchip also introduces an emulator strategy, implementing a modular emulator that allows the CPUs to emulate themselves. This approach means that the company need not create a special emulator for each microcontroller product. The base emulator contains a master PIC16C1XX and a socket for the device you wish to emulate. The master emulator device controls the emulation memory accesses and fetches and executes the instruction sequence from the emulation memory. All peripherals are on the slave emulator device. The slave device is the microcontroller product that the emulator places in a special operating mode. In this mode, the CPU core within the slave device goes into sleep mode, and the master CPU takes control of the peripherals. The CPU on the master emulator and the peripherals in the slave device communicate through a few control signals and an 8-bit bidirectional data bus, which is one of the 8-bit ports on the slave and a re-creation of the port on the master. Although Microchip won't offer PIC16C1XX products until the fourth quarter, a simulator will be available in the first quarter to allow you to begin development.

Microchip Technology Inc, Chandler, AZ. 1-602-786-7668, www.microchip.com.

Gigahertz attenuator gives you 15-dB range in 1-dB steps

Designed for operation from dc to 2 GHz, Alpha Industries' AD210-25 attenuator IC uses four switched resistive blocks in 1-, 2-, 4-, and 8-dB sequence to let you cut signal power from 0 to 15 dB in 1-dB steps, not including insertion loss. You control the internal switches of this GaAs monolithic-microwave IC FET, which targets cellular-phone and similar applications in which signal levels must be controlled, using parallel 0/­5V digital signals.

The 16-lead SO-package device has a maximum insertion loss of 1.8 dB at 900 MHz and 2.5 dB at 2 GHz. VSWR is less than 1.8-to-1 over the full frequency range for this 50V component. Its attenuation repeatability is ±25 dB plus 5% of the setting value, and third-order intercept point is 48 dBm at 500 MHz. Maximum power-handling capability for the AD210-25, which costs $4.40 (10,000), is 2W above 500 MHz and 0.5W at 50 MHz.

Alpha Industries Inc, Woburn, MA. 1-781-935-5150, fax 1-617-824-4564, www.alphaind.com.

1G-sample/sec ARBs generate true white noise and jitter

Arbitrary-waveform generators (ARBs) have long been able to generate pseudorandom noise. Now, however, Tektronix is offering one- and two-channel, 10-bit-resolution, 1G-sample/sec units that it claims are the first to also generate truly random white noise. Built-in analog and digital filters let you bandlimit the noise. The units offer a waveform memory of as much 4 Mbytes/channel and the ability to substitute a 10-bit-wide digital-pattern output for an analog output. Moreover, the units can simulate jitter with timing resolution as fine  as 2 nsec. For testing of disk drives and communications devices, menus let you select data streams containing 20 industry-standard-shape isolated-bit pulses.

An internal DSP and built-in FFT editor let you tailor the digital-filter characteristics to your needs. Built-in timing and state-table editors provide further flexibility in waveform definition. Real-time sequencing of pattern segments extends the effective waveform-memory depth be-yond that of the internal memory. Prices for the single-channel AWG 510 start at $21,995; those for the two-channel AWG 520 start at $28,995.

Tektronix Inc, Beaverton. OR. 1-800-426-2200, www.tek.com/Measurement.

Data-acquisition system introduces modules within VXI modules

Racal's ProDaq is a C-size VXI data-acquisition module that accommodates smaller mezzanine modules. The rather large C-size is the most popular VXI form factor. Since VXI's 1987 introduction, however, levels of integration have increased, enabling individual modules to hold more functions or more channels. Too often, though, a module contains unneeded functions or channels, resulting in an uneconomical system. Therefore, some vendors have opted for smaller modules, such as VXI's B-size or the relatively new CompactPCI. Racal, however, is sticking with C-size because of its popularity. For flexibility, the company has created a single-slot-width module that is, in effect, a backplane for as many as eight smaller modules, enabling users to order units configured for their needs. Despite the large number of multivendor mezzanine-bus standards, Racal has come up with its own. The company is convinced that  its architecture is superior to the others and intends to keep the 80-MHz internal bus proprietary.

An $1895 6700-series VXI module accommodates 392 digital I/O channels, 192 analog-input channels, or 128 analog outputs. The mezzanine modules in the initial offering are a $995, 48-channel digital-I/O unit; a $1695, 24-channel, 16-bit analog-input (A/D) unit; and a $1695, 16-channel analog-output (D/A) unit. You can synchronize data capture across multiple mezzanine modules and, with an appropriate VXI controller, you can transfer data to and from the main board at 16 Mbytes/ sec.

Racal Instruments Inc, Irvine, CA. 1-800-722-2528, 1-714-859-8999, fax 1-714-859-7139, helpdesk@racalinst.com, www.racalinst.com.

RF, automatic ID references help you sort through choices

A trio of reference materials from AIM-USA, the trade association of the automatic-identification and data-capture industry, helps you evaluate trade-offs of the various implementations of radio-frequency-identification (RFID) and other identification techniques, such as bar codes and magnetic stripes.

The $19.95 Source Provider Evaluation Guide contains work sheets with questions you should ask potential vendors about needs, technologies, capabilities, system integration, support issues, and costs. It also has a directory of AIM members, contact information, and brief descriptions of their capabilities. Another $19.95 reference, Radio Frequency Identification--Features, Facts, and Forecasts, briefly examines some of the technical basics of RFID, along with some case studies, and contains a directory of RFID providers that is a subset of the listing in the evaluation guide.

The $29.95 AIDC Sourcebook surveys all automatic-IC technologies with case histories, evaluation guidelines, and vendor information. This book is in many ways a superset of the other two, and you may find it the most useful.

AIM-USA, Pittsburgh, PA. 1-412-963-8588, fax 1-412-963-8753, www.aimusa.com.

Rugged system enclosure targets telecomm applications

Featuring a 15-slot, passive ISA backplane, the IPC-615 enclosure includes fault-detection features and a rugged design that suit mission-critical applications, such as telecomm systems. A 300W power supply handles both backplane power and a front-panel-accessible drive bay that holds a mixture of 3.5- and 5.25-in. peripherals. The front panel also houses dual 86-ft³/minute cooling fans and a removable air filter. Fan sensors detect failure of the cooling system, and temperature sensors detect excessive internal heat. Either event illuminates warning LEDs and sounds an audible warning. Available in desktop and 19-in. rack-mount models, the enclosures sell for $695.

Advantech, Sunnyvale, CA. 1-408-245-6678, www.advantech-usa.com.

Calendar

FPGA '98, Monterey, CA, offers sessions on new architectures, technology mapping for FPGAs with and without embedded RAM, multi-FPGA systems and other reprogrammable architectures, partitioning and floorplanning, fault detection and fault tolerance, fast CAD tools, time-multiplexed FPGAs, novel applications; and programmable architectures with special features. Registration costs $400 if you register before Feb 6 and $470 after Feb 6. Special rates apply for members of the Association for Computing Machinery and the Special Interest Group on Design Automation. FPGA '98, Meeting Hall Inc, Hamden, CT. Fax 1-203-287-9555 or e-mail Debbie Hall at deborah.hall@snet.net.

Microprocessor seminar series, Boston (and Feb 25 to 26 in Austin), explores Intel's products from its x86 to its IA-64 technologies. This seminar looks at Intel's x86 product road map and how it delivers newer generations of chips, given its fab capacity and cost structure. The seminar examines Intel's IA-64 transition and what it means. Another seminar examines the merit and business prospects of the processor options for PCs. Analysis includes Intel's Pentium and P6 families, Cyrix's MediaGX and 6x86MX, AMD's K6, Digital's Alpha family, and Power PCs. The Austin program presents an additional seminar on evaluating mPs for embedded applications. Registration costs $595 for one seminar and $1045 for two seminars. MicroDesign Resources, Sebastopol, CA. 1-707-824-4004.

Design, Automation, and Test in Europe--Conference and Exhibition, Paris, addresses all aspects of research and development of technologies for the design and test of electronics-based products. The event comprises paper, plenary, and hot-topic sessions; hands-on tutorials; a user's forum; vendor presentations; an exhibition; and more. The user's forum offers a designer's track with user-oriented sessions and provides information on new products, industrial-design methods, practical design experience, economy, and risk analysis. European Conferences, Edinburgh, UK. +44-131-225-2892, fax +44-131-225-2925.

Upgrade enhances thermal-analysis software

Flotherm Version 2 is a substantial redesign by Flomerics of its electronic thermal-analysis software. Most significantly, Version 2 includes a graphical user interface that allows you to create, edit, and manipulate data in a CAD-like environment.

You can now highlight and edit all objects and boundary conditions using mouse control. Three main application windows--Project Manager, Drawing Board, and 3-D Visualization--provide three ways of viewing and manipulating thermal models. All windows interact dynamically, so that model changes you make in one window directly affect the other windows. This arrangement gives great flexibility in manipulating the model.

The Project Manager window provides a hierarchical view of a thermal model, with all data pertaining to a particular object or subassembly visible in one display. The Drawing Board window provides a geometry-creation capability that enables you to graphically define objects with a mouse. The Visualization window provides 3-D graphics using the OpenGL graphics standard to perform functions such as zoom, pan, rotate, pan-in-zoom, and walk-through. An optional animation module, Flomotion, creates moving 3-D images of particle tracks and heat flux paths, which help you interpret results and convey information to colleagues. You can create thermal models for parts such as axial fans, heat  sinks, enclosures, and circuit boards by using parameter-driven menus. A radiation model also automatically calculates view factors between surfaces.

Flotherm Version 2 also provides interpretation and simplification of imported geometry from MCAD software such as Pro/Engineer, I-Deas, and Solid Designer. Flotherm Version 2 runs under Unix and Windows NT. Annual licences start at $19,500/£11,818.

Flomerics, Hampton Court, UK. +44 181 9418810, www.flomerics.com.

Modular architecture builds wireless baseband IC

The OneC Global System for Mobile communications (GSM) IC platform from VLSI Technology is a single-chip wireless baseband design with a modular architecture that you can customise. The OneC GSM uses VLSI's building foundation, the Standard Communication Platform, which is a universal wireless-development environment that can combine multiple standards. You can customise this chip for GSM mobile phones and related applications,   such as mobile computing, personal digital assistants, and global positioning systems.

The architecture of the OneC allows proprietary modifications such as a radio interface, system firmware, and extended functionality. OneC features include low power dissipation that typically provides 500-hour standby time or 7-hour talk time on a 3.6V 1200-mAhr battery; an on-chip package-oriented data service for high-speed General Packet Radio Services and multislot data, which eliminates the need for external processing and the need for a PCMCIA card; and a board area of 12312 mm with 144/176-FPBGA packaging.

The Standard Communication Platform accommodates standards such as PHS, DECT, GSM, and CDMA, allowing you to develop products for multiple markets based on a common architecture and tools environment. The Standard Communication Platform also allows you to develop firmware and software on one platform, making the software reusable. The Platform comprises building blocks that include both the VLSI-enhanced Vector ARMThumb RISC processor core and the Vector OAK DSP core, functional system blocks, DSP firmware, analogue cells, and a range of development and debugging tools. The IC provides speech coding for all defined GSM algorithms, including enhanced full rate, full rate, and half rate.

--by Brian Kerridge

VLSI, Munich, Germany, +49 89 627060, fax +49 89 62706 101, www.vlsi.com.

CCD-camera chip set consumes 500 mW

The MC-1 three-device multimedia camera chip set from Sony Semiconductor performs all CCD driving and signal functions for multimedia OEMs. All the key system elements  of the MC-1 chip set operate from 3.3V and create compact camera designs with a power consumption of less than 500 mW.

A CXD3123R signal processor with built-in A/D and D/A converters is at the heart of the chip set. This processor generates the sync signal needed by the colour CCD and performs the luminance- and chroma-signal processing for NTSC camera systems. The signal processor produces analogue Y/C output and two types of digital output; 16-bit YUV, which meets CCIR601 requirements; and an 8-bit YUV multiplexed output. The signal-processing functions operate with colour CCDs that range from 1/5-in. devices with 180k-pixel resolution to 1/4- and 1/6-in. devices at 250k-pixel resolution.

You can use either the 5V CXA-2006Q or the 3.3V CXA2096N processor-based chip set as the CCD-camera head amplifier. These processors combine a high-gain AGC amplifier for the CCD signal with a gain-control amp for the low-band chroma signal. The CXA2006 has a blanking function for calibrating the black level of the CCD output signal. The chip set also has the CXD1267AN single-chip vertical CCD driver with the timing-control functions for NTSC systems. The chip set costs $35 (10,000).

Sony Semiconductor, Basing-stoke, UK, +44 1256 478771, www.sony.co.jp.

DC/DC converter has 4.9 million-hour MTBF

The PKH extended design of Ericsson Components' MacroDens dc/dc power modules brings proven 4.9 million-hour MTBF to 5 to 7W dc/dc converters in an industry-standard 231-in. form factor. The single- and dual-output PKH modules use central pin connections and deliver full power of as much as 708C ambient. The modules offer pin-compatible upgrades for existing designs.

The PKH dc/dc converters use a custom-designed control IC, together with a thick-film ceramic hybrid substrate to reduce component count to 20. This move provides an overall height of 12.5 mm. The design also includes facilities such as remote-control pin on request.

The PKH converters meet requirements for pin-for-pin compatibility for existing through-board designs but have a migration route to SMD versions for future designs. The modules start at $27 (500).

Ericsson Components, Kista, Sweden. +46 8 721 7045, www.energy.ericsson.se.

New verification tool has a formal air

Synopsys, best known for its logic-synthesis tools, has added a gate-level verification tool, the Formality formal equivalence checker. You use an equivalence checker to exhaustively verify whether two representations of the same design are logically equivalent. An advantage of formal-verification tools over traditional event-driven or cycle-based simulation tools is that formal verification, like static-timing analysis,   requires no vectors.

Formality first checks whether a synthesized, gate-level design is equivalent to the presynthesis RTL representation of the design. You then reuse the tool after any design operation that adds or deletes logic functionality, such as adding scan-testability circuitry or modifying a clock tree. Unlike some other equivalence checkers based on a single equivalence solver, Formality has many solvers. During design analysis, the tool applies the solver best suited for a design structure. This feature increases total verification speed, which is orders of magnitude faster than gate-level, vector-based simulation. A hierarchy-management feature in the tool lets you compare designs that may be logically equivalent but have mismatched design hierarchies.

A gate-level schematic debugger helps you isolate mismatches that Formality finds. The tool highlights problems on the schematic but does not automatically go from the schematic to the problem code in the HDL file. Also, when you find an error between circuit representations, Formality cannot tell you how to correct the problem; that redesign step is up to you.

Formality uses Verilog, VHDL, or EDIF data. The tool is tightly coupled with Synopsys' Design Compiler logic-synthesis tool. This coupling lets you use Formality with more than 350 ASIC-synthesis libraries that support Synopsys tools. On the other hand, if you use a tool other than Design Compiler for logic synthesis, you probably do not want to use Formality for equivalence checking. Formality, running on Unix-based workstations, costs $100,000. (For additional information on formal-verification tools, see "Chip verification: a formal affair?" EDN, Jan 1, 1998, pg 85.)

--by Jim Lipman

Synopsys, Reading, UK. +44 1734 313822.

Precision PCI reset generator hits triple play

Any power-supply monitor for PCI designs has to be both fast and accurate while babysitting three supplies. The LTC1536 from Linear Technology puts 5 and 3.3V voltage monitors and a third adjustable monitor into an eight-pin MSOP device with threshold accuracy of 0.75%. The IC generates a reset signal within less than 500 nsec if any power rail falls more than 500 mV below specification and within 100 nsec if the 5V rail drops below the 3.3V rail by more than 300 mV. Drawing just 100 mA typical supply current, the LTC1536 provides reset operation for the 5 and 3V rails to as low as 1V.

You can also manually initiate a reset via a pushbutton input. By pushing the button for less than 2 sec, you cause the IC to generate a 100-msec "soft" reset, which is useful for designs that must detect the presence of transients and reset the CPU while not affecting DRAM; holding it down for more than 2 sec causes the device to produce, on a separate IC output pin, a 200-msec "hard" reset signal that is equivalent to a power-fail/power-on reset.  The LTC1536 costs $2.65 (1000); a similar device, the LT1326, costs $2.20 (1000), and targets non-PCI applications but requires just a 20-mA supply current.

Linear Technology Corp, Camberley, UK. +44 1276 677676, www.linear-tech.com.

Vantis opens the gate to FPGAs

Vantis, the programmable-logic subsidiary of AMD (Sunnyvale, CA), enters the market for high-gate-count FPGAs with the SRAM-based VF1 family. VF1 devices have 12,000 to 36,000 logic gates. Additionally, the devices integrate 3584 to 6144 bits of high-speed RAM, which the company does not include in its logic-gate counting. Vantis optimized the RAM and associated dedicated logic for dual-port configurations (one read and one read/write) and divided it into 128-bit (3234-bit) blocks.

VF1's variable-grain architecture is conceptually reminiscent of the flexible granularity of QuickLogic's (Sunnyvale, CA) pASIC2 and pASIC3 antifuse FPGAs. The lowest level building block, a microcombinatorial element, or mCE, comprises a three-input look-up table and decoding logic. Two mCEs plus a multiplexer form a configurable combinatorial element (CCE). Add a configurable sequential element (CSE) (essentially, a D flip-flop plus decoding logic), and you get a configurable building block (CBB).

Up one level in the hierarchy is the variable-grain block (VGB), comprising four CBBs plus carry, wide gating, and control logic. Each VGB can implement one function with as many as 16 inputs, two functions with as many as eight inputs, or four functions with as many as four inputs. Four VGBs combine to form a "Super VGB," which can if necessary implement one 32-input function. Vantis adapted its 0.25-mm, four-layer-metal process from AMD's K6 mP. This process provides an abundance of variable-length inter- and intra-VGB interconnect resources to help you wire everything together. Four dedicated clock networks span the chip, and the I/O buffers include separate input and output registers and several user-programmable options. Vantis even includes on-chip 200-MHz PLLs in two corners of the die.

Robust EDA support is essential to insulating VF1 architectural complexity from end users and enable them to exploit its capabilities. Vantis reports that it has worked closely with third-party schematic-entry, synthesis, and simulation vendors. At product introduction, the company also hopes to ship beta front-end device libraries, back-end map, and place-and-route software as well as 66-MHz PCI initiator and target firm cores. The company plans production-software support and sampling of the 25,000-gate VF1025 for the end of the second quarter of this year. The $46 VF1012 commercial-temperature version comes in a 144-pin TQFP. The VF1020 and VF1036 will follow in the third quarter.

Vantis Corp, Sunnyvale, CA, USA. +1-408-732-0055, fax +1-408-774-8461, www.vantis.com.

Unusual technology yields 500-MHz-bandwidth analog storage scope

Analog-scope technology is alive and well, and it still yields impressive products at competitive prices. To prove it, Iwatsu has announced the TS-8500, a $12,495, four-channel (two channels with full attenuators), 10-trace unit, with 500-MHz bandwidth and a writing rate of 5 div/nsec.

The specs alone say that this is not your father's analog scope, but the fact that the scope uses unusual technology unavailable in your father's day is not immediately obvious. Unlike virtually all other scopes, analog and digital, the screen is not the CRT. The scope uses a 2-in.-diameter scan-converting storage tube inside to drive the 5.5-in.-diagonal LCD on which you view waveforms. According to Iwatsu, the result is the highest brightness level ever in analog scopes.

Two channels provide 2-mV/div sensitivity and both 50V and 1-MV inputs. The other two channels provide 100 and 500 mV/div and 1-MV sensitivity. Display modes include normal, X-Y, and expanded-sweep. The scope has dual timebases and provides full delayed-sweep operation. As with many analog scopes, you can add channels 1 and 2 (those with high sensitivity and full attenuators), and you can invert Channel 1. The combination of inverting and adding creates, within limits, a differential input.

Iwatsu America Inc, Carlstadt, NJ, USA. +1-201-935-8486, fax +1-201-935-8533, iwatsu@access.digex.net, www.iwatsu.com.

Add wizardry to your core-based programmable-logic designs

Max+Plus II, Altera's programmable-logic-design tool suite, now includes the MegaWizard shell for developing customized logic cores. You use MegaWizard to optimize a parameterized function, described in an HDL, for a specific application without modifying HDL code.

For every core in MegaWizard, the core developer (either Altera or a third-party vendor) has written a program defining the graphical user interface (GUI) you use to parameterize the core. The GUI is platform- and tool-independent and lets you display a schematic symbol for the function and a list of parameters you can set. When you compile the core in MegaWizard, the synthesis engine in Max+Plus II creates the required core functionality with your parameter values.

You can use MegaWizard on library-of-parameterized-module (LPM) functions, including arithmetic operations, counters, and multiplexers. Working with its core partners in the Altera Megafunction Partners Program, Altera will develop future MegaWizard shells, including FFT, PCI, and DSP functions for cores in the MegaCore library. Prices for Max+Plus II with  MegaWizard are $995 to $4995, depending on features and capability.

Altera, High Wycombe, UK. +44 1494 602000, www.altera.com.

µC family expands performance and memory range

Microchip's PICmicros, based on a Harvard architecture, make it easy to add instruction bits because the program and data memory are different sizes. The new PIC16C1XX family, which outperforms the company's high-end PIC17CXX family, has 16 address bits and a linear address space for as much as 4 Mbytes of program memory and 4 kbytes of data memory. Using a 16-bit instruction width, the PIC supports 68 instructions (an increase from the 56 on the PIC17CXX), including a single-cycle 838-bit multiply. In addition, the device has 65 single-word instructions. Despite the change in instruction width, the PIC16C1XX is source-code-compatible with the PIC16CXX. The new architecture also supports three 12-bit data pointers with five addressing modes.

Using a 10-MHz external crystal, the PIC16C1XX has a 100-nsec instruction cycle. An internal four-phase clock multiplier allows peripherals to run at 40 MHz. The PIC16C1XX has a 32-word-deep hardware stack, an increase from eight and 16 deep on other family members. The PIC16C1XX also includes a software stack to better support high-level languages, such as C. Microchip claims that its new architecture is about 30% better than its previous architecture for handling C code. The company also improved the PIC's interrupt capability by adding a fast interrupt mode for external or internal interrupts. The fast interrupt performs hardware-context saving using shadow registers. A bit in the return-instruction operation code tells the CPU whether to return from an interrupt using the shadow or the regular stack.

With the PIC16C1XX, Microchip also introduces an emulator strategy, implementing a modular emulator that allows the CPUs to emulate themselves. This approach means that the company need not create a special emulator for each microcontroller product. The base emulator contains a master PIC16C1XX and a socket for the device you wish to emulate. The master emulator device controls the emulation memory accesses and fetches and executes the instruction sequence from the emulation memory. All peripherals are on the slave emulator device. The slave device is the microcontroller product that the emulator places in a special operating mode. In this mode, the CPU core within the slave device goes into sleep mode, and the master CPU takes control of the peripherals. The CPU on the master emulator and the peripherals in the slave device communicate through a few control signals and an 8-bit bidirectional data bus, which is one of the 8-bit ports on the slave and a re-creation of the port on the master. Although Microchip won't offer PIC16C1XX products until the fourth quarter, a simulator will be available in the first quarter to allow you to begin development.

Microchip Technology Inc, Bourne End, UK. +44 1628 851077, www.microchip.com.

Gigahertz attenuator gives you 15-dB range in 1-dB steps

Designed for operation from dc to 2 GHz, Alpha Industries' AD210-25 attenuator IC uses four switched resistive blocks in 1-, 2-, 4-, and 8-dB sequence to let you cut signal power from 0 to 15 dB in 1-dB steps, not including insertion loss. You control the internal switches of this GaAs monolithic-microwave IC FET, which targets cellular-phone and similar applications in which signal levels must be controlled, using parallel 0/­5V digital signals.

The 16-lead SO-package device has a maximum insertion loss of 1.8 dB at 900 MHz and 2.5 dB at 2 GHz. VSWR is less than 1.8-to-1 over the full frequency range for this 50V component. Its attenuation repeatability is ±25 dB plus 5% of the setting value, and third-order intercept point is 48 dBm at 500 MHz. Maximum power-handling capability for the AD210-25, which costs $4.40 (10,000), is 2W above 500 MHz and 0.5W at 50 MHz.

Alpha Industries Inc, Woburn, MA, USA. +1-781-935-5150, fax +1-617-824-4564, www.alphaind.com.

1G-sample/sec ARBs generate true white noise and jitter

Arbitrary-waveform generators (ARBs) have long been able to generate pseudorandom noise. Now, however, Tektronix is offering one- and two-channel, 10-bit-resolution, 1G-sample/sec units that it claims are the first to also generate truly random white noise. Built-in analog and digital filters let you bandlimit the noise. The units offer a waveform memory of as much 4 Mbytes/channel and the ability to substitute a 10-bit-wide digital-pattern output for an analog output. Moreover, the units can simulate jitter with timing resolution as fine  as 2 nsec. For testing of disk drives and communications devices, menus let you select data streams containing 20 industry-standard-shape isolated-bit pulses.

An internal DSP and built-in FFT editor let you tailor the digital-filter characteristics to your needs. Built-in timing and state-table editors provide further flexibility in waveform definition. Real-time sequencing of pattern segments extends the effective waveform-memory depth beyond that of the internal memory. Prices for the
single-channel AWG 510 start at $21,995; those for the two-channel AWG 520 start at $28,995.

Tektronix Inc, Marlow, UK. +44 1628 403300, www.tek.com/Measurement.

Data-acquisition system introduces modules within VXI modules

Racal's ProDaq is a C-size VXI data-acquisition module that accommodates smaller mezzanine modules. The rather large C-size is the most popular VXI form factor. Since VXI's 1987 introduction, however, levels of integration have increased, enabling individual modules to hold more functions or more channels. Too often, though, a module contains unneeded functions or channels, resulting in an uneconomical system. Therefore, some vendors have opted for smaller modules, such as VXI's B-size or the relatively new CompactPCI. Racal, however, is sticking with C-size because of its popularity. For flexibility, the company has created a single-slot-width module that is, in effect, a backplane for as many as eight smaller modules, enabling users to order units configured for their needs. Despite the large number of multivendor mezzanine-bus standards, Racal has come up with its own. The company is convinced that  its architecture is superior to the others and intends to keep the 80-MHz internal bus proprietary.

An $1895 6700-series VXI module accommodates 392 digital I/O channels, 192 analog-input channels, or 128 analog outputs. The mezzanine modules in the initial offering are a $995, 48-channel digital-I/O unit; a $1695, 24-channel, 16-bit analog-input (A/D) unit; and a $1695, 16-channel analog-output (D/A) unit. You can synchronize data capture across multiple mezzanine modules and, with an appropriate VXI controller, you can transfer data to and from the main board at 16 Mbytes/ sec.

Racal Instruments Inc, Slough, UK. +44 1628 604455, helpdesk@racalinst.com, www.racalinst.com.

RF, automatic ID references help you sort through choices

A trio of reference materials from AIM-USA, the trade association of the automatic-identification and data-capture industry, helps you evaluate trade-offs of the various implementations of radio-frequency-identification (RFID) and other identification techniques, such as bar codes and magnetic stripes.

The $19.95 Source Provider Evaluation Guide contains work sheets with questions you should ask potential vendors about needs, technologies, capabilities, system integration, support issues, and costs. It also has a directory of AIM members, contact information, and brief descriptions of their capabilities. Another $19.95 reference, Radio Frequency Identification--Features, Facts, and Forecasts, briefly examines some of the technical basics of RFID, along with some case studies, and contains a directory of RFID providers that is a subset of the listing in the evaluation guide.

The $29.95 AIDC Sourcebook surveys all automatic-IC technologies with case histories, evaluation guidelines, and vendor information. This book is in many ways a superset of the other two, and you may find it the most useful.

AIM-USA, Pittsburgh, PA, USA. +1-412-963-8588, fax +1-412-963-8753, www.aimusa.com.

Rugged system enclosure targets telecomm applications

Featuring a 15-slot, passive ISA backplane, the IPC-615 enclosure includes fault-detection features and a rugged design that suit mission-critical applications, such as telecomm systems. A 300W power supply handles both backplane power and a front-panel-accessible drive bay that holds a mixture of 3.5- and 5.25-in. peripherals. The front panel also houses dual 86-ft³/minute cooling fans and a removable air filter. Fan sensors detect failure of the cooling system, and temperature sensors detect excessive internal heat. Either event illuminates warning LEDs and sounds an audible warning. Available in desktop and 19-in. rack-mount models, the enclosures sell for $695.

Advantech, Sunnyvale, CA, USA. +1-408-245-6678, www.advantech-usa.com.

Calendar

FPGA '98, Monterey, CA, offers sessions on new architectures, technology mapping for FPGAs with and without embedded RAM, multi-FPGA systems and other reprogrammable architectures, partitioning and floorplanning, fault detection and fault tolerance, fast CAD tools, time-multiplexed FPGAs, novel applications; and programmable architectures with special features. Registration costs $400 if you register before Feb 6 and $470 after Feb 6. Special rates apply for members of the Association for Computing Machinery and the Special Interest Group on Design Automation. FPGA '98, Meeting Hall Inc, Hamden, CT, USA. Fax +1-203-287-9555 or e-mail Debbie Hall at deborah.hall@snet.net.

Microprocessor seminar series, Boston (and Feb 25 to 26 in Austin), explores Intel's products from its x86 to its IA-64 technologies. This seminar looks at Intel's x86 product road map and how it delivers newer generations of chips, given its fab capacity and cost structure. The seminar examines Intel's IA-64 transition and what it means. Another seminar examines the merit and business prospects of the processor options for PCs. Analysis includes Intel's Pentium and P6 families, Cyrix's MediaGX and 6x86MX, AMD's K6, Digital's Alpha family, and Power PCs. The Austin program presents an additional seminar on evaluating mPs for embedded applications. Registration costs $595 for one seminar and $1045 for two seminars. MicroDesign Resources, Sebastopol, CA, USA. +1-707-824-4004.

Design, Automation, and Test in Europe--Conference and Exhibition, Paris, addresses all aspects of research and development of technologies for the design and test of electronics-based products. The event comprises paper, plenary, and hot-topic sessions; hands-on tutorials; a user's forum; vendor presentations; an exhibition; and more. The user's forum offers a designer's track with user-oriented sessions and provides information on new products, industrial-design methods, practical design experience, economy, and risk analysis. European Conferences, Edinburgh, UK. +44-131-225-2892, fax +44-131-225-2925.

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