February 2, 1998

Scheme yields frequency-locked triangle waves

Daniel Dufresne, Decatron, St Bruno, PQ, Canada

The circuit in Figures 1 and 2 generates frequency-locked triangle waves of constant amplitude. It uses readily available TTL and other older-technology parts.  The circuit portion in Figure 1 comprises the frequency dividers, counters, and converter. The portion in Figure 2 contains current sources, output circuits, and comparators. The circuit satisfies a need for a triangle wave of approximately constant amplitude, at a frequency exactly one-tenth or 1/100 that of an input TTL clock. The input frequency can vary over a wide range before the circuit loses lock. The triangle-wave output frequency ranges from 250 Hz to 2.5 kHz. Two decade dividers divide the input clock by 10 or 100. Switch S₁ selects the divider ratio. The signal RISE/FALL is a 50%-duty-cycle wave that turns on a 2I current source, comprising transistors Q₃, Q₄, and Q₅; a ­I current source comprising Q₁ and Q₂ is always on.

After you initially adjust R₂₁, op amp IC₃ keeps any dc offset (caused by tracking imbalances between the current source and sink) to a minimal value. The output signal from the 8-bit DAC, IC₁₂, controls the current level in both the source and sink. The currents sum on capacitor C₂, thus generating a triangle wave. An op amp buffers the triangular signal; potentiometer R₂₂ adjusts the output level. Assuming a fixed input frequency and a fixed capacitor value, you can adjust the current sources for the desired amplitude.

If the frequency decreases, the triangle-wave amplitude increases. To keep the amplitude constant, comparator IC₄ detects that the positive-peak amplitude is too high. The comparator sends input-clock signals to decrement the 8-bit counter IC₆ and IC₇, thus controlling the source- and sink-current value through the DAC. Similarly, if you raise the clock frequency, the triangle-wave amplitude decreases. Comparator IC₅ detects that the positive-peak amplitude at the end of the triangle wave's rise is too low. IC_11a latches the comparator output and gates clock pulses to increase the count and the source- and sink-current values.

If you run out of counts on IC₆ and IC₇, the carry and borrow output signals trigger the monostables, IC_13A and IC_13B. LED D₂ or D₃ lights to warn you to change the input frequency accordingly. Frequency tracking is asymmetric: As soon as the circuit detects the high limit, pulses decrement the counter. The sooner the high limit occurs, the more decrementing pulses the counter receives. However, you detect that the current is too low only when the RISE/FALL signal falls, and the triangular wave is still below the positive-peak low limit. This occurrence triggers a single pulse.

To adjust the circuit, set the divider to f/10, apply a 10-kHz TTL signal to the clock input, short-circuit C₂, push the TEST button, and adjust R₂₂ for a zero-centered triangular wave. Release the TEST button, and remove the short circuit. You can increase the frequency range by using a bigger counter and a higher resolution DAC or by band-switching the current-summing capacitor, C₁, with some added logic that the borrow and carry outputs of IC₇ trigger.

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