February 16, 1998

Termination techniques for high-speed buses

Karthik Ethirajan and John Nemec, PhD, California Micro Devices

Choosing the proper bus-termination technique--parallel, series, Thevenin, ac, or diode-based--is critical to digital-system performance. Improper termination can lead to ringing and stair-stepping, which in turn can cause false triggering and data errors.

As bus speeds continue to increase, system designers must seriously consider the issues of signal propagation and quality. Concerns previously relegated to the analog world, such as transmission-line effects, now determine whether a digital design will work at such high signal-transmission and edge rates. High-speed pc-board traces behave like transmission lines, and reflections occur at all points on the pc-board trace where impedance mismatches exist.

In a typical digital system, the output impedance of the driver is less than the characteristic impedance of the pc-board trace, which is in turn less than the input impedance of the receiver. Reflections translate into observable effects, such as ringing and stair-stepping. These distortions can produce or contribute to a number of problems: false triggering in clock lines; erroneous bits on data, address, and control lines; an increase in clock and signal jitter; and an increase in total emissions from the pc board. An effective way to reduce the above transmission-line effects is to properly terminate these lines.

Common passive-termination techniques include parallel, Thevenin, series, and ac terminations. Schott-ky-diode termination, which is an unconventional passive-termination technique, also provides some advantages. Familiarity with each technique's relative merits and demerits helps you choose the best technique or techniques for your board or system. Selection guides list recommended termination techniques for various common digital-system scenarios and for standards and specifications (Tables 1 and 2).

Parallel termination

Parallel termination is the simplest termination technique: A resistor, R, connects the open, or load, end of the transmission line to ground or V_CC (Figure 1). The value of R must match the characteristic impedance, Z₀, of the line to eliminate reflections. If R matches Z₀, the termination resistor absorbs the energy that causes the reflection, regardless of the value of the termination voltage (see box "Theory of terminations"). In digital logic, the sinking current is typically greater than the sourcing current. Terminating to V_CC helps the driver's sourcing capability, and terminating to ground helps its sinking capability. Hence, terminating to V_CC is better than terminating to ground, assuming a 50% duty cycle.

The advantages of parallel termination are that it offers simplicity of design and application and that it requires only one additional component, although you may ultimately use two resistors to terminate both ends of the line. The disadvantages of this technique are that dc power dissipates in the termination resistor, which is typically 50 to 150 ohms, and that constant dc current from the driver at high or low logic levels adds to the dc load of the driver. Also, parallel termination degrades the high-output level of the signal. Terminating TTL outputs to ground lowers the V_OH level, which reduces the noise immunity at the receiver input.

Parallel termination also results in a lower signal slew rate with a capacitive load than does an unterminated line. The load capacitance and the resistance (parallel combination of termination resistance and Z₀) add to the RC time constant of the signal, which rises to the driver's output voltage. Note that the voltage at the end of an unterminated line doubles and hence produces a faster slew rate. The effect of different termination techniques on the slew rate of the signal at the end of the line is the outcome of complex interactions between the transmission line and the RC delay involved.

When you use parallel termination, you should be aware that a line impedance of less than 100 ohms terminated with this scheme requires a dc output of 24 mA for TTL levels (V_OH(MIN)=2.4V). For this reason, parallel termination is not recommended for a battery-driven system. Also, note that the termination resistor dissipates as much as 0.25W (50 mA through a 100 ohm resistor) of power, which a CMOS system that consumes only a few milliwatts of power can't accommodate. Also, remember that the power dissipation depends on the duty cycle: Connecting the resistor to ground results in the lowest power dissipation for low duty cycles, and terminating to V_CC results in the lowest power dissipation for high duty cycles (Reference 1). In addition, a strong pulldown resistor might cause the falling edge to be faster than the rising edge, resulting in the distortion of the duty cycle of the signal (Reference 2).

Thevenin termination

Thevenin, or dual, termination uses two resistors, R₁ and R₂ (Figure 2), whose parallel combination matches the Z₀ of the line. The Thevenin voltage, V_TH=V_R2, must be such that the driver's I_OH and I_OL currents are within the driver's specifications (see box "Design rules for Thevenin termination"). R₁ helps the driver to easily pull up to a logic-high state by sourcing some current to the load. Similarly, R₂ helps the driver to pull down to a logic-low state by sinking some current to ground. Properly chosen values for R₁ and R₂ enhance the driver's fan-out and smooth the power-dissipation variations because of the change in duty cycles.

The advantages of Thevenin termination are that, in this scheme, the termination resistors also serve as pullup and pulldown resistors and thereby improve the noise margin of the system. Thevenin termination also reduces the burden on the driver by supplying additional current to the load. This additional current helps the driver especially in a large voltage-swing system, such as 5 and 3.3V CMOS- or Bi-CMOS-based systems. Also, this type of termination provides good overshoot suppression.

One disadvantage of Thevenin termination is that a constant flow of dc from V_CC to ground, regardless of the logic state, results in static power dissipation in the termination resistors. This method also requires ratio resistors and additional power and ground connections. Also, a line voltage, which equals the Thevenin voltage on a tristated bus, close to the switching threshold voltage causes greater levels of power dissipation within CMOS logic devices. At a voltage close to the threshold, both NMOS and PMOS transistors are conducting, which results in a current path between V_CC and ground. Thevenin termination also results in a lower signal slew rate with a capacitive load than does an unterminated line. The load capacitance and the resistance (parallel combination of Z₀, R₁, and R₂) add to the RC time constant of the signal, which rises to the driver's output voltage.

Note that CMOS devices switch at 50% threshold. Hence, when using Thevenin termination for CMOS devices, equal values for R₁ and R₂ result in a line voltage of one-half the V_CC. This situation occurs when a logic device does not drive the line. The result is greater levels of power dissipation within the receiver. The sum of this dissipation and the power dissipation in the termination resistors may be unacceptably high for CMOS logic devices (Reference 1).

The best applications for Thevenin termination are TTL circuits, especially advanced Schottky families, such as FAST (Reference 3). You can also use Thevenin termination to provide proper ECL termination from the ­5.2V supply and for TTL from a 5V supply.

Series termination

Series termination, or back-matching, is a source-end termination unlike other types. A series termination comprises a resistor between the driver's output and the line (Figure 3). The sum of the output impedance of the driver, RD, and the resistor value, R, must equal Z₀. With this type of termination, only one-half the signal value appears on the line because of the voltage division between the line and the combination of the series resistor and the driver's impedance.

At the receiving end, however, the mismatch between the line impedance and the receiver's typically high input impedance causes a reflection of approximately the same voltage magnitude as the incident signal. The receiving device immediately sees the full voltage (the sum of the incident and reflected voltages), and the added signal propagates to the driving end. However, no further reflections occur because the series resistor terminates the reflected wave at the driving end.

The advantages of series termination are that it adds only one resistor per driver for the system and that its termination resistor consumes less power than all the other resistive types of termination. Series termination also adds no dc load to the driver and offers no extra impedance from signal line to ground.

The disadvantages of series termination are that using this method makes it difficult to tune the value of the series resistance so that the received-signal amplitude (after the first reflection) falls within the switching threshold and noise budget. Also, most drivers are nonlinear; that is, the output impedance varies with the logic state of the device, further complicating tuning. Hence, it is difficult to select a crisp value for the series resistance by applying the simple design equation.

Another disadvantage of series termination is that the driving end of the transmission line does not see the full reinforced signal amplitude for as long as twice the propagation delay of the line. The diminished signal amplitude during this time reduces some of the receiver's noise immunity in a multidrop situation. Also, with series termination, the data setup time for digital signals of the receiver (part of its timing budget) must accommodate this propagation delay. Series termination also results in a lower signal slew rate with a capacitive load than does parallel termination. The load capacitance and the Z₀ of the line add to the RC time constant of the signal, which rises to one-half the driv-er's output voltage.

The applications for series termination include CMOS-to-CMOS connections because series termination adds no impedance from signal line to ground (Reference 1). This termination also works well for advanced CMOS logic families, such as FACT and ECL. With FACT devices, the series-termination resistor adds to the output impedance of the driver. Thus, the driver dissipates less power than it does without the termination (Reference 3). Series termination also works well for systems with loads lumped at the end of the cable as opposed to a multidrop situation. In a multidrop situation, receivers on the line see the full amplitude of the signal at different times.

You can eliminate the disadvantages of higher propagation delay and usage with lumped loads only by using more transmission lines (Reference 4). If the driver has high fan-out, then you can connect many transmission lines--N, for example--to the driver's output. Each line then needs its own series termination according to the design equation. The net impedance at the output of the driver is (R+Z₀)/N. This net impedance must be much larger than the internal impedance of the driver for the driver itself to function.

AC termination

AC, or RC, termination comprises a resistor, R, and a capacitor, C, that connect to the load end of the transmission line (Figure 4). The value of R must match the Z₀ of the line to eliminate reflection. Choosing the capacitor value is intricate, because a small value results in a smaller RC time constant, and the resulting RC circuit acts as an edge generator, causing overshoot and undershoot. On the other hand, a large capacitor value increases power consumption. As a rule, the RC time constant must be greater than twice the loaded propagation delay of the line (Figure 4 and Reference 5). Power dissipation in the termination components is a function of the frequency, duty cycle, and bit pattern of the previous data. These factors affect the charging and discharging of the termination capacitor and hence affect power dissipation.

The advantages of ac termination are that the termination capacitor blocks dc and hence saves considerable power and that an appropriate choice of the capacitor value results in the waveform at the load end that's nearly an ideal square wave with minimal overshoot or undershoot.

One disadvantage of ac termination is that the data on the line may exhibit time jitter, depending on the previous data pattern. For example, a long string of like bits causes the line and capacitor to charge to the maximum level of the driver's output voltage. Then, a subsequent data bit of the opposite polarity takes longer than normal to cross the receiver threshold because the voltage at the receiver starts from a greater potential. The timing budget must include this increased time to guarantee system operation (Reference 3).

When using ac termination, note that the standard RS-422 interface protocol does not recommend ac termination, because the drivers' typical 100 ohm source impedance can introduce output jitter. Also, current-mode drivers do not use ac termination (Reference 3).

Schottky-diode termination

Schottky-diode, or diode, termination comprises two Schottky diodes and their connections (Figure 5). Any reflection at the end of the transmission line, which causes the voltage at the input of the receiver to rise above V_CC plus the forward-bias voltage of the diode, forward-biases the diode that connects to V_CC. The diode turns on and clamps the overshoot to V_CC plus the threshold voltage.

Similarly, the diode that connects to ground limits undershoot to its forward-bias voltage. However, the diodes absorb no energy and merely divert it to either the power or ground plane. As a result, multiple reflections occur on the line. The reflections gradually subside, principally because of the loss of energy via the diodes to V_CC or ground and the resistive losses of the line. These losses limit the amplitude of the reflections to maintain signal integrity.

Three characteristics of a diode have a profound effect on its performance as a termination device. Higher turn-on time, t_ON, results in undershoot. Higher forward-bias voltage, V_F, causes time jitter. Higher reverse-recovery time, t_rr, increases the rise time, t_r, of the signal. Thus, you can preserve signal integrity by using a diode that has a small t_ON, V_F, and t_rr as a termination device. A Schottky diode possesses these characteristics.

One advantage of diode termination is that, unlike a classic termination scheme, Schottky-diode termination requires no matching. Hence, you can use this technique to terminate a line of unknown Z₀. If the load that  connects to the transmission line is capacitive, then it effectively reduces Z₀. Variations in Z₀ do not affect the termination. Also, the power dissipated in the dynamic on-resistance of the Schott-ky diode is much smaller than the power dissipation of any resistive-termination technique. In fact, the reflection power partially feeds back to the source through the forward-biased diodes. Also, you can place Schottky diodes at any point along the line where reflections may originate.

The one disadvantage of diode termination is that the existence of multiple reflections can affect subsequent signal launches. Hence, you need to verify diode response at the switching frequency. To reap the benefits of this termination scheme, you must choose a Schottky diode that has small t_ON, V_F, and t_rr.

Schottky-diode termination works well in a multidrop situation in which some of the receivers on the line can also drive the line. Hence, application of transmission-line theory to arrive at a conventional termination in such situations becomes highly complicated. Simulations prove that terminating at multiple points--preferably at points of discontinuity, or stubs--yields a uniformly improved signal integrity over the length of the bus.

One general point applies to all of these termination schemes: The effective Z₀ of a transmission line decreases because of layout procedures and loading in a multidrop situation (Reference 5). The actual loaded characteristic impedance, Z₀', is now as follows:

where C₀ is the intrinsic capacitance of the trace, and C_D is the distributed capacitance of the receiving devices (the total load capacitance divided by the trace length). Typically, sockets add 2 pF to C_D, and vias add 0.3 to 0.8 pF to C_D. Hence, a distributed capacitive load on a line reduces the characteristic impedance. This correction factor for Z₀ applies to all termination schemes, depending on the overall system architecture.

References

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17. USB Specification, Revision 1.0, January 1996.

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