March 13, 1998

WHAT'S HOT IN THE DESIGN COMMUNITY

Innovative µP core uses MIPS IV architecture

With its new VR5400 µP-core family employing the MIPS architecture, NEC parlays MIPS licensees' ability to take the basic instruction-set architecture and redesign a core to deliver the desired price/performance point. Although Sandcraft (Sunnyvale, CA), a developer of "chipless"-µP intellectual property, codeveloped the VR5400 with NEC, NEC has exclusive rights to the architecture. Starting with the MIPS IV instruction set and the R5000's cache and MMU, these companies designed a symmetrical, dual-issue, superscalar architecture. Most ALU operations are single-cycle, so the pipelines typically do not interlock and stall. However, when the instruction issue unit pairs a single-cycle instruction with a longer instruction, a pipeline stall may occur. But if the next pair of instructions is also a single-cycle/long-instruction combination, the VR5400 dynamically swaps the instructions and avoids interlocking. Each pipeline has a local bypass that allows information to bypass the write-back stage, feeding data directly back into the pipeline and preventing pipeline locking. The VR5400 also supports global bypassing that would allow the two pipelines to exchange results to help minimize the effects of data dependencies.

Unlike the superscalar R5000, which has separate integer and floating-point pipelines, the VR5400's pipelines can handle either integer or floating-point instructions. This approach means that the core can execute any combination of integer and floating-point instructions: integer-integer, integer-floating, and floating-floating. To enable each pipeline to handle  both integer and floating-point operations, NEC split floating-point operations: The mantissa goes through the integer portion of the pipe, and the exponent goes through a separate 12-bit ALU. The VR-5400 complies with the IEEE-754 floating-point format.

Within the two pipelines, the VR5400 has two unified integer/floating-point units, a nonblocking load/store unit, a 32×32-bit integer/floating-point multiply unit with a 64-bit accumulator, a vector unit that supports an 8×8-byte SIMD (single-instruction multiple-data), and a branch unit. Each integer/floating-point unit contains a 64-bit barrel shifter that can perform single-cycle left or right rotation of 32 or 64 bits. This feature is useful for data alignment in graphics and printer applications. NEC also adds a set of rotation instructions to support the barrel shifting.

The load/store unit allows pipeline flow to continue when no data dependencies exist. Through NEC's addition of a data-prefetch instruction, the load/store unit can prefetch data to fill the cache without affecting the pipeline. (That is, no pipeline locking occurs.) Also, to minimize data dependencies, the VR5400 can dynamically swap instructions among pipelines so that consecutive instructions can flow down the same path.

The multiply unit can perform continuous 32×32-bit, single-cycle multiplies and multiply-accumulates without stalling the pipeline; however, a 64×64-bit multiply may stall the pipeline. The vector unit uses 64-bit registers that are shared floating-point registers, so the device cannot simultaneously perform floating-point and vector operations; in most applications, this constraint is not an issue. You have to flush the pipeline when switching between floating-point and vector operations, but you need not perform a time-consuming context switch. To reduce code size and in-crease performance, the VR5400 adds register-based multiply instructions; this addition allows the CPU to write the multiply result to a register file instead of to special internal registers, as the standard R5000 does.

The VR5400's cache structure, similar to the R5000, comprises a 32-kbyte instruction cache and a 32-kbyte data cache. Both are two-way set-associative and use a least recently used replacement algorithm. The caches use a 32-byte line. You can lock the caches on a per-line basis; this approach benefits time-critical instruction loops, interrupt handlers, and data. For example, you may use line locking to lock critical data structures, such as programming stack and global variables as information passes between subroutines. Although a normal load from cache takes only one cycle, filling a cache line takes eight cycles, even with zero-wait-state memory. The data cache also supports write-back and -through cache protocols.

The bus protocol supports four outstanding reads for concurrent instruction- and data-cache refills and supports split reads with write-back or store operations. The VR5400 collects consecutive uncached word-write operations to form a single block-write operation; this approach is the same as data merging, except that the collection approach requires you to align the data on a line boundary. The VR5400 can also perform burst reads as large as the cache line.

The VR5400's MMU supports ad-dress translation, facilitates exception processing, and manages operating modes. It is compatible with the R5000's MMU. It supports 36-bit physical and 64-bit virtual addresses with variable page size from 4 kbytes to 16 Mbytes. It has a 48 dual-entry translation-look-aside buffer, which maps into 96 pages.

NEC offers a companion $35 (10,000) chip set that supports PCI, memory control, a DMA controller, an interrupt controller, a timer, and serial and parallel ports. NEC also offers a $1000 evaluation board for the VR5464. Hewlett-Packard (Colorado Springs, CO) offers logic-analyzer support using the N-Wire debugging port of the VR5400. N-Wire provides access to internal states and offers execution control. You can use the logic analyzer to set multiple hardware breakpoints on instruction and data addresses or on data values. Cygnus (San Jose, CA, www.cygnus.com), Green Hills (Santa Barbara, CA, www.ghs.com), and Apogee (Campbell, CA, www.apogee. com) provide compiler support for the VR5400. Wind River (Alameda, CA, www.windriver.com) and Integrated Systems (Sunnyvale, CA, www.isi.com) offer RTOS support.

The first two devices in the VR5400 family are the VR5432 and VR5464. The VR5432 has a 32-bit system interface, runs at 167 MHz, comes in a 208-pin PQFP, and costs $45 (10,000). The VR5464 has a 64-bit system interface and comes in a 272-pin advanced-BGA (ABGA) package, a multilayer technology that allows more complex connectivity between the die and the pins. The VR5464 comes in 200- and 250-MHz versions and costs $70 and $95, respectively. Both devices operate at 2.5V internally with 3.3V I/O. At 250 MHz, the VR5464 consumes 4.5W and has SPECint95 and SPECfp95 ratings of 10 and 5, respectively. NEC also offers the VR5400 as a core for integration into  a custom product.

--by Markus Levy

NEC Electronics Inc, Santa Clara, CA. 1-800-366-9782, www.nec.com.

Make way for the graphics Goliath

Intel's long-awaited Intel740 graphics chip is now available for sampling. The company developed the chip with Real3D (Orlando, FL), a former division of Lockheed Martin. The Intel740 implements the full 533-Mbyte/sec peak bandwidth AGP 2x bus, including sideband signaling. Deep request buffering, direct main-memory execution, plus the ability to simultaneously access local frame-buffer memory all reduce the AGP latency effects of multiple system operations contending for core-logic attention.

The Intel740 combines 2-D, 3-D, and video support along with an integrated 220-MHz RAMDAC in one chip and targets the high end of the $1500 to $2500 desktop-PC market. Intel claims that the chip can sustain 425,000- to 500,000-triangle/sec and 45 million- to 50 million-pixel/sec performance. Thus, the company contends that the device outperforms first-generation, high-end, 3-D-only accelerators. Per-pixel interpolation enhances quality, and the 64-bit, 3-D parallel-processing engine boosts performance. Local frame-buffer-memory options include 100-MHz synchronous DRAM or synchronous graphics RAM in 2- to 8-Mbyte densities, although the Intel740 does not support storing texture-map data in the frame buffer. Other key pieces of the company's platform include the 440LX AGP chip set and Pentium II processor, which handles 3-D, front-end-geometry operations.

One surprising feature, given the requirement to store texture maps only in main memory, is the small, 256-byte on-chip texture cache. Intel claims that this size is adequate because of the fast AGP interfaces and tiled addressing mode, which exploits pixel spatial locality. Brooktree/Rockwell's (Santa Clara, CA) Bt829 and Bt869 complete the video-in and -out capability, Hauppauge Computer Works (Hauppauge, NY) supplies a TV-tuner chip, and C-Cube (Milpitas, CA) and Zoran (Santa Clara, CA) handle hardware digital-versatile-disk (DVD) support. Intel's benchmarking indicates that under "average" loading conditions, a 266-MHz Pentium II processor, along with Zoran's software DVD decoder, can smoothly render 24-frame/sec video at 24-bit color and 720×480-pixel resolution. The Intel740 comes in a 468-bump BGA, and Intel builds the 3.3 million-transistor chip on its mainstream 0.35-µm process. For graphics add-in cards, Real3D developed an AGP-to-PCI adapter chip that also supports texture-map storage in additional local memory.

Intel-supplied Direct3D and Open-GL drivers let you use the Intel740 in Windows 95 and Windows NT 4.0 environments. For Windows 95, Intel developed the AGP support that Microsoft bundles in OSR 2.1. Intel includes NT 4.0 AGP software with the graphics drivers. Although you cannot ignore Intel's numerous abilities to influence the Intel740's fortunes, the success of this chip is not guaranteed. Workstation users and game players may still be willing to pay more for the slight performance edge of a dedicated 3-D accelerator with on-chip rendering. (Speed-seeking software developers often write directly to the hardware instead of to an application-programming interface.) The Intel740 costs $34.75 (10,000)--probably too expensive for the fast-growing market for PCs costing less than $1000, and business PC applications for 3-D graphics have not yet emerged. Intel's upcoming Katmai processor with its multimedia-extension-enhanced floating-point performance also threatens to further reduce graphics-chip-set prices and required features. At this year's Intel Developers Forum, Senior Vice President Albert Yu alluded to upcoming low-end P6-generation CPUs with integrated graphics controllers.

--by Brian Dipert

Intel Corp, Folsom, CA. 1-916-356-8080, fax 1-916-356-6227, www.intel.com.

Keep your LCD bright with boost/inverter bias supply

LCD screens require a relatively high-voltage bias supply, which your system must usually derive from a low-voltage source. Maxim's MAX686 boost dc/dc converter can deliver as much as 27.5V or ­27.5V (at 10 mA) from a 2.7 to 5.5V supply. The 16-pin QSOP device uses a current-limited, PFM-control technique, switching as fast as 300 kHz, to achieve efficiencies as high as 93%. You need not add an external switch because the IC includes an internal N-channel MOSFET. To set the output voltage, you control a 6-bit, built-in DAC using up/down control lines. Typical quiescent current is 65 µA, and current consumption in shutdown mode is 1.5 µA for this $2.95 (1000) IC.

--by Bill Schweber

Maxim Integrated Products, Sunnyvale, CA. 1-408-737-7600, fax 1-408-737-7194, www.maxim-ic.com.

New 2.5V logic family debuts with 16-bit devices

The 2.5V VCX logic family is the latest addition to Pericom Semiconductor's line of SiliconInterface products, which includes the FCT3, LPT, LCX, and ALVCH logic families. The VCX family supports low-voltage µPs and synchronous DRAMS that are moving to 2.5V power supplies. Pericom's VCX ICs feature a patented 3.6V I/O tolerance for use in mixed 1.8 to 3.3V systems; 5V-tolerant parts are also available. Devices in the VCX family also have a three-state balanced output drive of 24 and ­24 mA and a static power consumption of 20 µA. The typical propagation delay is less than 2.5 nsec, and the VCX family also includes edge-rate control to reduce ground bounce and ring-back.

All VCX products are available in 48-pin TSSOPs. The VCX16244A/16245A costs $2.05 (1000), and the VCX-16373A/16374A costs $2.15 (1000).

--by Stephen Kempainen

Pericom Semiconductor, San Jose, CA. 1-408-435-0800, fax 1-408-435-1100, www.pericom.com.

Lossless compression core hits 100 Mbytes/sec 

Some computer architects have long viewed lossless data-compression technologies as the answer to incessantly growing demand for more storage and higher transfer rates. Unfortunately, except for modems and tape drives, the use of data compression has been limited to software-based schemes that maximize disk capacity. Theoretically, however, you could embed a compression IC with the controller in a disk drive and--without help from an operating system--increase storage capacity and data rate by a factor of 2, 4, or possibly 8. Taking the technology a step further, a data-compression engine that operates between a µP and main memory could offer similar advantages in effective memory capacity and data rate. BTG USA claims to have developed a compression core that can fit in these roles as well as in network switches, set-top boxes, and other media-rich applications.

Several factors--starting with throughput and latency--have conspired to limit the use of hardware-based data compression. However, BTG's X-Match processor, which Simon Jones, PhD, developed at Loughborough University (Loughborough, UK, www.lboro.ac.uk), delivers a 100-Mbyte/sec stream through the compression engine and a 140-Mbyte/sec stream through the decompression engine. Moreover, 4-byte words pass through the compression processor with a latency of two µP clock cycles. Leading disk-drive companies have also claimed that hardware compression in a disk drive requires operating-system support for variable-sized drives. Theoretically, however, drive designers could embed the compression technology using conservative compression ratios and hide the technology from the host CPU. In fact, compression could allow drive vendors to offer relatively larger disk drives and higher data rates without stressing the read channel and head/ media interface that typically limit drive designs.

The high data rates of the X-Match algorithm result from a dictionary-style compression engine that simultaneously operates on 4 bytes. The wide words re-duce the number of matches in a data stream but result in a compression ratio of 33-to-3 bits when a match occurs. To further boost efficiency, the engine can also achieve compression when partial matches occur and can dynamically reorder its dictionary based on real-time statistics, thereby maximizing compression ratios.

BTG currently offers an X-Match Evaluation Kit that includes an FPGA implementing the compression processor. The kit also in-cludes some sample applications and technical support. For designers who want to integrate the X-Match engine into an OEM product or to design an X-Match IC for resale, BTG licenses the VHDL source code starting at $35,000 and negotiates the actual price and royalties on an application-by-application basis.

--by Maury Wright

BTG USA Inc, Gulph Mills, PA. 1-610-278-1660, www.btg-et.com.

MMX single-board computer measures only 5.75×8 in.

Aaeon Technology's single-board computer targets designers seeking the features of a full-blown PC in a small package for embedded applications. The PCM-5894 supports a range of processors, including Intel's (Santa Clara, CA) Pentium CPUs up to the 233-MHz P55C with multimedia-extension (MMX) instructions, AMD's (Sunnyvale, CA) K5/K6, and Cyrix's (Richardson, TX) M1/M2. Two onboard 72-pin SIMM sockets house as much as 128 Mbytes of system memory, and a video accelerator interfaces CRTs or flat-panel displays, including 36-bit thin-film-transistor LCDs. M-Systems' (Newark, CA) DiskOnChip flash disk provides as much as 72 Mbytes of read/write storage and system-boot-up capability in a 32-pin DIP package. Communications circuitry includes three RS-232C and one RS-232C/422/485 ports (four 16C550 UARTs), two USB connectors, and 100BaseT Ethernet. A floppy-disk and enhanced-IDE controller, a multimode parallel port, and keyboard/mouse interfaces round out the board's I/O capability. The PCM-5894 includes both a PC/104 connector for 16-bit bus expansion and a PCI-slot connector. The system requires 5V at 10A, depending on the CPU, and 12V. The PCM-5894 single-board computer costs $450 (one to nine).

--by Warren Webb

Aaeon Technology Inc, Hazlet, NJ. 1-732-203-9300, fax 1-732-203-9311, www.aaeon.com.

GaAs devices hurdle some obstacles
to 10-Gbps optical links

The path to truly high-speed fiber-optic links, which combine several slower signals into one OC-192 channel, requires basic functions, such as channel multiplexers, demultiplexers, and timing-recovery and data-decision circuits. Oki now provides these functions via a group of GaAs ICs that you can use as building blocks for a 10-Gbps system that you build using 64 OC-3, 155-Mbps data streams. Eight such OC-3 links combine into a 1.25-Gbps OC-24 stream; eight of these streams combine into a 10-Gbps stream.

Four functions are now available. On the transmitting side, the KGL4201 8-to-1 multiplexer has 50 ohms, direct dc-coupled data and clock inputs and ac-coupled data and clock outputs. The 40-pin impedance-controlled package operates from 2V, dissipating 2.4W. At the receiver, the complementary KGL4202 1-to-8 demultiplexer uses dc coupling for all inputs and outputs, except for the ac-coupled clock input, a 2V device requiring 3.2W. To extract the 10-Gbps clock from the received-data stream, you can use the GHDD4411 exclusive-OR device, a 50 ohm, 28-pin IC, which operates at 20 Gbps from just 1.5V, dissipating 0.6W. The 20-Gbps GHDD4414 decision circuit with phase detectors strips data from the OC-192 bit stream by using the extracted clock, additionally providing an analog phase-variation output; the 50 ohm I/O IC operates from 1.5V and consumes 1W. These devices cost less than $2000 (moderate volumes).

--by Bill Schweber

Oki Semiconductor, Sunnyvale, CA. 1-408-720-1900, fax 1-408-720-1918, www.okisemi.com.

Shrinking silicon, more accurate
software boost performance

Lucent Technologies is now offering samples of its first backward-compatible 0.25-µm-based ORCA 2T family member, the OR2T15A. Higher gate-count OR2T40A and OR2T60A FPGAs will be available for sampling in the second quarter. One benefit of the process conversion is performance: The new "-7'' speed bin touts 1.1-nsec look-up-table delays and 6.4- to 8-nsec clock-to-valid-output timings. The other compelling advantage is continued cost reductions. For example, the projected fourth-quarter price for OR2T15A-2 is $17.45 (50,000), more than 50% lower than the July 1997 price. Actual prices depend on the device, speed bin, package, and your order volume and introduction time frame.

This generation of 0.25-µm FPGAs retains a 3.3V operating voltage, whereas many other FPGAs built on similar lithographies require a 2.5V supply for the logic core. However, Lucent plans to move to 2.5V in the future to obtain even better performance. The 0.25-µm process also forms the foundation of the company's upcoming ORCA 3 devices.

All of the ORCA 2T speed potential goes to waste if the back-end technology mapping and place-and-route tools can't accurately model the FPGAs. As logic delays decrease, signal skew resulting from routing plays an increasing role in defining overall device performance. Previous generations of Lucent's ORCA Foundry software used a simple but imprecise, worst-case, lumped-sum estimation of routing impedance. Foundry 9.15, now available, uses distributed impedance techniques, which better predict the silicon's performance potential. Foundry 9.2 and Lucent's 50-MHz PCI master/ target core, both available this month, will add support for the ORCA 2T "-7'' speed bin.

--by Brian Dipert

Lucent Technologies, Allentown, PA. 1-610-712-4331, fax 1-610-712-4209, www.lucent.com.

Calendar

March 24 to 26

Automated Manufacturing Exposition, Greenville, SC, features robotics, design engineering, technology transfer, and more. Approximately 300 exhibitors present products in robotics, design, hydraulics and pneumatics, computer technology, automatic identification, materials handling, control systems, and engineering design for manufacturing. On-site registration costs $15. Technical Expositions and Conferences Inc, Columbia, SC. 1-803-772-8262.

March 25 to 27

Windows Hardware Engineering Conference (WinHEC) '98, Orlando, FL, presents seminars; keynotes; forums; exhibits; and presentations on new initiatives, standards, and technologies for Windows platforms. The conference addresses issues for building the best products using new technologies and taking advantage of new capabilities in Windows 98 and NT 5.0. Topics include digital-TV and other consumer technologies, designing for the new, low-cost market segment, multimedia and 3-D, making systems manageable, lowering the cost of ownership, and Microsoft's plans for moving Windows NT to the consumer space. Registration before March 16 costs $1145; on-site registration costs $1345. WinHEC, Denver, CO. 1-303-813-4245.

March 31 to April 2

Embedded Systems Conference Spring, Chicago, covers software and hardware integration, management, and testing. The event features 87 classes and tutorials on adaptations of PC technology for embedded systems, building in Web functionality, project management, and design-for-test methodology. Seven full-day sessions offer topics including real-time performance, programming languages, and fuzzy logic for automotive applications. Software topics include C, C++, Windows CE, Java, and real-time kernels. The conference features 67 top industry experts and more than 170 exhibitors. Miller Freeman Inc, San Francisco, CA. 1-415-538-3848.

Quintet of 3.6V power amps mesh
with cell-phone demands

As cell phones for the various bands migrate to sub-3.6V-only operation from a lithium-ion cell or a pack of nickel-metal-hydride cells, system designers prefer components that operate directly at these lower voltages rather than requiring voltage doublers. Linear power amplifiers in cell-phone and industrial, scientific, and medical (ISM)-band applications have been among the last devices to go "low voltage," but a set of single-supply power amplifiers from Triquint Semiconductor changes the situation. The company's five GaAs power amplifiers, each complying with a different cell-phone standard and also adaptable to ISM systems minimize power consumption and space needs.

For Global System for Mobile communications (GSM) applications, you can choose between the TQ7541 for 1710- to 1785-MHz European DCS-1800 specifications and the TQ7641 for the 1850- to 1910-MHz US PCS-1900 requirements. Both offer 32-dBm output, and minimum efficiencies for the 7541 and 7641 are 40 and 37%, respectively. Cell phones supporting Ad-vanced Mobile Phone Services (AMPS) IS-19 and TDMA IS-136 operation in the 824- to 849-MHz band can use the TQ7121 with 50% AMPS efficien  cy; phones supporting TDMA PCS for 1850- to 1910-MHz operation can use the TQ7621. The TQ7111 targets use in AMPS IS-19 operation from 824 to 849 MHz; it too boasts a minimum efficiency of 50%. You can use the devices with 3 to 5V supplies.

All five devices have 50 ohm matched inputs, contain their own negative-bias-voltage generator via a 12-MHz charge pump, and need minimal external circuitry for matching and bias bypassing. Built-in sequencing logic signals that the negative bias is operating and stabilized and thus that the power amplifiers are ready for operation. Triquint fabricates the power amps in a new MESFET process and packages them in standard-handling plastic TSSOP-20s. The unique internal mechanical design couples with an integral "downset-paddle" thermal pad on the package's bottom to provide low package-source inductance as well as a thermal impedance of 12ºC/W.

--by Bill Schweber

Triquint Semiconductor Inc, Hillsboro, OR. 1-503-615-9000, fax 1-503-615-8900, www.triquint.com.

Pixel processor yields two-chip camera

Digital-camera designers can now move a step away from the long-envisioned single-chip camera. Rockwell has just announced a pixel-processor IC that includes a USB interface and an interface to the Common Intermediate Format (CIF), 352×288-pixel CMOS imager introduced in January. The pixel processor also leverages a proprietary compression algorithm that allows 30-frame/sec traffic to travel across the USB while the 12-Mbps interface supports only 7.5-frame/sec uncompressed traffic. The Rp0352 pixel processor costs $8 (100,000), and the CMOS Ri0352P passive pixel sensor costs $18 (100,000). Rockwell offers a number of other passive and active CMOS imagers with resolutions as high as 960×720 pixels at prices of $18 to $63.

--by Maury Wright

Rockwell Semiconductor Systems, Newport Beach, CA. 1-714- 221-6996, www.rss.rockwell.com.

Designers advance in the quest for the perfect MOSFET

Because battery life becomes increasingly important as systems get smaller, designers are looking for the ideal power-supply MOSFET--having 100% efficiency and 0 ohm R_DS(ON), among other specifications. The FDS6680A from Fairchild Semiconductor moves closer to that ideal, with maximum 9.5-mohms R_DS(ON) at V_GS of 10V, along with typical gate charge of 37 nC.

These 30V, 12.5A n-channel de-vices--fabricated in a trench process to keep capacitance constant per unit area while on-resistance decreases--are available in eight-lead SOIC packages and have high switching speeds, commensurate with the approximately 300-kHz speeds that PWM switching applications require. On-delay, rise, off-delay, and fall times are 8,  32, 42, and 14 nsec, respectively, for the FDS6680A MOSFETs, which cost $1.75 (1000).

These devices join Fairchild's new FDR4420A MOSFET, a 30V, 11A device with 9-mohm R_DS(ON) and 41-nC typical gate charge for switching at approximately 1 MHz. This unit comes in an eight-pin SuperSOT, which is 38% smaller than a conventional SOP.

--by Bill Schweber

Fairchild Semiconductor, Sunnyvale, CA. 1-408-822-2152, fax 1-408-822-2104, www.fairchildsemi.com.

Satellite-broadcast down-converter IC skips IF

Philips Semiconductors' TDA8060, a "zero-IF" QPSK down-converter IC for digital satellite-broadcast receivers, eliminates the need for IF stages by directly processing the output signal from a satellite dish. This arrangement allows you to design receivers for DVB or DBS systems without the need for mixer, bandpass filter, and IF amplifier stages; the arrangement typically reduces designs from five to three chips.

Another design advantage includes elimination of IF alignment and IF frequencies as interference sources. This feature improves on earlier designs, which needed shielding precautions to reduce the number of errors in MPEG video and audio data, particularly under poor signal conditions. Another useful feature of the IC is easier EMC qualification by virtue of lower radiated emissions.

You can apply the TDA8060 to designs operating in the 950-MHz to 2.2-GHz range. The BiCMOS 24-pin SSOP part costs approximately $2 in volume.

­­by Brian Kerridge

Philips Semiconductors, Eindhoven, The Netherlands. Fax +31 40 10 458 9196, www.semiconductors.philips.com.

Call-waiting IC beats "talkoff" and "talkdown"

Consumer Microcircuits' CMX602A call-waiting identification IC for telephone systems overcomes the common problems of "talkoff" and "talkdown," as well as associated power and cost penalties, without using DSP. Talkoff occurs when the detector confuses a user's voice with the equipment alert signal (CAS). Talkdown occurs when a detector cannot sense the CAS in the presence of high levels of user voice signals.

The CMX602A meets British Telecomm and ETSI specifications for caller ID and call-waiting ID. The device performs against the Bellcore CIDCW specification without using internal DSP, and it requires no UART to interface with a mC. Packaged in a 16-pin SOIC, the CMX602A consumes 0.4 mA at 2.7V.

In addition, the EV6021 PIC-based evaluation kit enables you to develop on- and off-hook-type systems, both in feature-phone and adjunct-box modes. You can select between Bellcore and BT standards. The kit reports the number of local mutes and valid detects in the off-hook mode for feature phones; it also reports the number of times you take the connected phone off the line in adjunct-box configuration.

­­by Brian Kerridge

Consumer Microcircuits, Witham, UK. +44 1376 513833, www.cmlmicro.co.uk.

TriCore architecture attracts 15 companies

More than a dozen companies have announced support for designs using Siemens Semiconductors' TriCore 32-bit mC-DSP architecture. The 15 companies include Accelerated Technology, Ashling Microsystems, ETAS, Green Hills Software, HighTec, Hitex, Integrated Systems, Lauterbach, Microconsultant, Nohau, PLS, S&P Media, Syndesis, Tasking, and TECSI.

The support includes software development tools, debuggers, real-time operating systems, emulators, CASE tools, and consulting services. For questions regarding each company's products and applications, use the following contact information:

For general inquiries regarding TriCore:

Siemens Semiconductors, Munich, Germany. +49 89 722 275 15, www.siemens.com.

For CASE tools:

S&P Media, Bielfeld, Germany. +49 521 14503 250, www.sp-media.de.

For compilers:

Green Hills Software, Paris, France. +33 1 41 22 43 21, www.ghs.com.

For development environments:

Tasking, Southampton, UK. +44 1703 334774, www.tasking.com.

For emulators:

Hitex, Karlsruhe, Germany. +49 721 9628 126.

Nohau, Campbell, CA, USA. +1 408 866 1820.

For emulator/debuggers:

Ashling Microsystems, Limerick, Ireland. +353 61 334466, www.ashling.com.

Lauterbach, Hofolding, Germany. +49 8104 89430, www.lauterbach.com.

For ERCOS RTOS:

ETAS, Schweiberdingen, Germany. +49 711 811 8491.

For fast-view66/WIN development environment:

PLS, Lauta, Germany. +49 35722 3840.

For FLDE AutoStudio development environment:

Syndesis, Athens, Greece. +30 1 729 2985, www.flde.com.

For Matrix and BetterState:

Integrated Systems, Sunnyvale, CA, USA. +1 408 542 1500, www.isi.com.

For Nucleus Plus RTOS:

Accelerated Technology, Mobile, AL, USA. +1 334 661 5770, www.atinucleus.com.

For PXROS RTOS:

HighTec, Saarbrücken, Germany. +49 681 9 26 130, www.hightec-rt.com.

For RTOS:

TECSI, Paris, France. +33 1 47 78 67 67.

For training:

Microconsultant, Munich, Germany. +49 89 4506170, www.microconsult.com.

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