March 26, 1998

Chip place-and-route tools lay it on the line

Jim Lipman, Technical Editor

The final step in ASIC implementation is defining your chip's physical layout. With interconnect-dominated deep-submicron designs, the tools and techniques you use determine whether your design is successful.

After you check the logic functionality and simulate the timing of your digital-chip design, it's time to physically implement the design with a layout. This stage is when automated place-and-route (P&R) tools appear. The idea of connecting megagate chips with dozens of blocks, thousands of cells, hundreds of thousands of nets, and interconnect metal totaling a kilometer or more would be inconceivable without EDA P&R tools.

The number of commercial tools to place and route your chip is small, but products differ greatly in capability and price. Virtually all P&R tools do automatic routing, most with preroute block placement and timing constraints on at least some critical nets. Beyond this basic capacity, features expand to cover more complex routing for signal-integrity compliance, differential-pair matching, clock-tree synthesis, power-grid design, and very-high-gate-count chips. Understanding the features of available P&R tools and matching them with your chip's requirements saves you time and money when you're ready to go to silicon.

The P&R tools you choose depend on the kind of chip you're designing. Your design can be cell-based, gate-array, embedded-array, or full-custom. P&R tools for programmable-logic chips, specifically targeting coarse-grained FPGA or CPLD architectures, usually come from a programmable-logic vendor. These tools target the vendors' own programmable-logic chips (Reference 1).

Cell-based chips contain two types of logic blocks: standard-cell-based blocks and embedded cores. EDA tools generate standard-cell blocks from rows of logic cells, with wiring channels between adjacent cell rows. Embedded cores are soft or hard. A soft core is either in an HDL or is a netlist of library cells, optimized during implementation for a specific process. A hard core has a predefined layout for a target process and is embedded in a chip as a fixed block. Cell-based chips have all mask layers defined for a given chip.

A gate array is an array of predefined logic gates, including a power grid, but without defined logic interconnectivity. The manufacturer processes the array through local interconnect within the defined gates. When targeting a design, you define the gate array's signal routing between gates, and final-metallization processing implements these connections.

An embedded array combines cell-based and gate-array features. The chip comprises a gate array in which one or more cell-based cores substitute parts of the array of gates. The core vendor predefines the embedded cores, and you use the array to "personalize" chip logic around these cores. You can preprocess embedded-array chips until the stage at which the chip needs final metallization to interconnect the array's uncommitted gates and embedded cores for a design. This preprocessing is similar to that of gate arrays.

A full-custom chip has all or most of its circuitry "designed from scratch" for a design. Full-custom chips often contain timing-critical digital circuitry, analog circuits, or both. These types of chips, because of the critical nature of their embedded functions, are generally not amenable to full-chip automatic P&R tools. You can use a shape-based router for some portions of a full-custom chip layout, but most designers still do a large part of such designs manually (see box "Shape-based routing enhances constraint management", on pg 76).

Wire-dominated designs

Deep-submicron chips are interconnect-centric. This fact means that the wire parasitics between transistors, rather than transistor-delay characteristics, dominate performance. Chip performance refers not only to delay times between nodes on the chip, but also to a variety of other parameters that affect how well your chip works or even if it works at all. Wire length influences chip timing and maximum clock speed. Wire-route congestion helps determine chip size and yield. Route spacing and quality affect signal skew and crosstalk. Wire width affects signal delay and chip reliability due to electromigration problems, particularly on clock and power nets. The ability of P&R tools to handle these types of problems varies widely from vendor to vendor.

You need different types of P&R tools for different types of chip implementations. For example, gate-array routing requires different algorithms than does cell-based routing (Table 1). In addition, the type of routing tool needed for detailed intracell routing is different than the tool you use for chip assembly (see box "Channel vs area routing," pg 75). Assembling the blocks on a chip means connecting a relatively small number of cores, memories, and user-defined logic blocks (Figure 1). A typical chip-assembly router has to handle as many as 50 blocks, each block with as many as several hundred connecting points, or pins, on several layers of metal interconnect. The maximum nets that a chip-assembly router addresses are on the order of 10,000 to 20,000.

Interblock routing tools address a different problem. These tools may have to connect thousands of individual cells, each with just a few connecting points, on one or two metal layers. Problems associated with special nets, such as clock lines and power grids, are smaller with intracell routers than with chip-assembly tools.

P&R constraints

Deep-submicron (0.5 µm and below) chip P&R is more than just placing cells and blocks in a minimum area and connecting the appropriate pins. With stringent timing specifications for many chips, P&R tools are generally timing-driven. This factor means that you can control routing with signal-delay limits on critical nets. P&R tools vary widely in how many nets can have timing constraints. The more constraints placed on the router, the longer the router takes to finish a job and the greater the possibility that the router will not complete all routes (some constraints may be impossible to meet).

Routing today's high-speed chips requires more than just routing timing constraints. You also have to meet many other electrical specifications, including signal integrity, electromigration limits, and power dissipation (Reference 2). Although all popular chip routers are timing-driven, few are signal-integrity-driven as well. Silicon Valley Research links SonIC, its cell-based P&R tool, to its Analog Tool Box, bringing analog-circuit simulation into the routing operation. Analog Tool Box provides a means of interactively checking routed lines for crosstalk and other signal-integrity problems. IC Craftsman from Cadence, on the other hand, is a shape-based router that is both timing-driven and signal-integrity-driven (see box "Shape-based routing enhances constraint management"). You use IC Craftsman for full-chip assembly and a Cadence routing tool, Silicon Ensemble, for block routing.

Startup company Everest Design Automation is developing a shape-based tool that you can use for both block routing and chip assembly. Besides being a unified tool for all levels of cell-based routing, Everest's Wire Wizard will be available for both Windows and Unix platforms. Two other companies, Snaketech and Tanner Research, offer this dual-platform flexibility in chip-routing tools.

Router limitations

The major problem with today's chip P&R tools is the hierarchy inherent in core-based chips. Chips with embedded blocks have two major hierarchical levels, one within the blocks themselves and another for the entire chip containing the blocks. As previously noted, the different parameters and constraints needed for core or block routing vs those associated with full-chip assembly often require different routing.

Jon Levi, development-support manager of product development, and Charley Kahle, technical director, both of Cadence Spectrum Design (the design and design-support group of Cadence), summarize the deficiencies of available chip routers. Being responsible for many high-density, high-speed chip designs, Levi and Kahle agree that although many current chip routers do an efficient job on "flat" (no physical hierarchy) designs, core-based chips present problems. Blockages in embedded cores prevent globally routed wires from traversing these cores, thus wasting silicon area. Furthermore, clock-tree synthesis is more difficult for core-based designs than for flat designs. You really need two levels of synthesis: one for cores and another for the top-level chip. Meeting critical clock constraints, such as latency and skew, becomes much more difficult with two levels of clock-tree synthesis.

A number of designers who perform chip P&R bring up what they consider to be a serious problem regarding timing-driven router accuracy. When you synthesize your design from an RTL to a gate-level representation, the synthesis tool uses a statistical wire-load model to meet timing constraints. A timing-driven router computes timing information based on wire length and parasitic information, with parasitic parameters based on a process-technology file. The inconsistency between synthesis- and router-timing models can cause difficulties in physically implementing the logic that the synthesis tool defines, resulting in additional work for the designer responsible for chip layout.

Another problem with current routers is that their interconnect-parasitic calculations are too inaccurate for chips processed at or below 0.25 µm. Automatic routers use 2-D estimations for wire parasitics; 3-D models would make the routing operation too lengthy for full chips. Some full-chip-analysis tools, such as those offered by Simplex Solutions (San Jose, CA, www.simplex.com), have more accurate parasitic-estimation algorithms, but these algorithms are too time-consuming for router use. The accuracy problems of today's routers make the use of full-chip verification tools an important part of your postlayout chip design (Reference 3).

There are several features that Kahle, Levi, and other cell-based-chip designers feel a router must have to be useful on high-speed designs. These features include wide-wire generation, clock synthesis, power-grid capability, and both timing and signal-integrity constraint-driven routing (Figure 2). Clean interfaces to other design tools, such as floorplanners, are also important. Floorplanning lets you place blocks and estimate chip timing before full routing, saving time that you might waste by routing a chip with less-than-optimally placed blocks. Keep all these points in mind when shopping for your chip P&R software

References

1. Dipert, Brian, "Shattering the programmable-logic speed barrier," EDN, May 22, 1997, pg 36.

2. Lee, Tsu-Chang and J Cong, "The new line in IC design," IEEE Spectrum, March 1997, pg 52.

3. Lipman, Jim, "Postlayout EDA tools lock onto full-chip verification," EDN, Oct 10, 1996, pg 93.

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