March 26, 1998

PLL implements FPGA-based SDRAM controller

Eddy Debaere, Barco Graphics, Ghent, Belgium

As FPGA capabilities increase and time to market decreases, FPGAs gain more acceptance for implementing both data and control paths. Thus, they find wide use as controllers and datapath glue logic for fast-page DRAMs. Synchronous DRAMs (SDRAMs), whose control signals use a clock input as reference, are a natural target for FPGA-based controllers. SDRAMs operate at frequencies of 100 MHz and higher (in contrast with fast-page DRAMs, for which a 60-MHz memory-system clock was considered high). Figure 1 shows a way to implement FPGA-based SDRAM controllers. Figure 2 shows the timing for a Xilinx XC4010E-2 device. You can apply the method to FPGAs from other vendors, as well as to high-frequency systems other than SDRAMs.

When you use FPGAs, delays to get on and off chip add up quickly: clock pin to internal clock buffer for the internal clock-distribution net (5.4 nsec) and internal clock to output flip-flop (4.5 nsec minimum). The sum of these delays excludes an FPGA from application with SDRAMs using a 10-nsec clock period, considering a 3-nsec setup time for the address, control, and data-out signals. Figure 1 shows how to use a PLL with an FPGA and how to implement clock and control-path signals to make FPGA-based SDRAM controllers that operate at 100 MHz and beyond. The SDRAM address, data, and control signals use the memory-system clock, MCLK, as reference and the FB signal from an FPGA output pin as feedback.

Because the PLL loop uses no dividers, MCLK and XCLK have the same frequency. When the PLL locks, the XCLK signal precedes MCLK by a time equal to the sum of the clock-buffer delay (from XCLK to ICLK) and the combinatorial output-buffer delay (from ICLK to the PLL feedback pin). The address, control, and data-out signals obtain their clock signals from ICLK. Because the delay from ICLK to the clocked output pin (7.0 nsec for the slew-rate-limited output) is close to but higher than the delay from ICLK to the FB output pin (4.8 nsec for a fast output), the clocked output appears early in the CLK period.

The required SDRA setup time is thus easily fulfilled in a 100-MHz system: (10­(7.0­4.8))>3 nsec. Note that changes in temperature, IC processes, and voltage have little influence on performance, because the XCLK clock-generating circuit is a closed-loop system. Moreover, the output buffer of the FB pin and the control and data pins have the same clock input as does the input pin, and all circuit blocks reside on the same die. Tests designed to check the data-input setup-and-hold times used a clocked input flip-flop (in the same I/O block as the data-output flip-flop), which received its clock from an internal version of MCLK. This configuration avoids excessive hold-time requirements for the SDRAM. (Editor's note: An EDN contributing editor warns that the 7.0­4.8 nsec reflects maximum specified times for the XC4010E-2 and yields an acceptable margin for an SDRAM with 1.5-nsec minimum hold time. However, an FPGA running at typical specs may present a marginal situation.) Tests using the AV9170-01 PLL from ICS show satisfactory performance to 106.25 MHz. (DI#2165)

Comparator uses signal-dependent hysteresis

P Krehlik and L Sliwczynski, University of Mining and Metallurgy, Krakow, Poland

Sometimes, you need to distinguish between two voltages, using some hysteresis in the decision. When the levels of the compared signals vary over a wide range (for example, a few orders of magnitude), the hysteresis width should vary similarly to ensure a constant ratio between hysteresis width and signal level. You could encounter such a situation, for example, when you need to decide which of two transmission channels conveys a "higher quality" signal (one with a higher level). You need the hysteresis to avoid permanent changes in the decision when the signal levels are close to each other. In this case, the best way to choose the greater voltage is to make the decision by taking the ratio of the signals instead of comparing them directly. Figure 1 shows a circuit with signal-variant hysteresis.

Amplifiers IC_1A and IC_1B with associated resistors and  diodes, R₁, R₂, D₁, and D₂, operate as logarithmic converters, producing output voltages

where V_T=kT/~;25 mV at room temperature, and I_S is the saturation current of the p-n junction. The derivation of the equation assumes that R₁=R₂=R. Next, voltages V_O1 and V_O2 combine in the summing amplifier, IC_1C.   Using the assumption that R₃=R₅ and R₄=R₆ and that the diodes are matched, the output voltage from IC_1C is

The voltage is thus proportional to the ratio of the input voltages. The last amplifier in the circuit, IC_1D, is a standard inverting comparator with hysteresis centered around zero and the threshold levels:

The voltage swing at the output of the circuit (V⁺_O4, V_+O4), is a function of the limiter comprising resistor R₉ and diodes D₃ to D₈. The output voltage, V_O4, changes state when V_O3>V⁺_H (output goes low) or V_O3<V⁼_H (output goes high). These conditions correspond to

The design allows you to distinguish between two signals, with a tolerance set by the external components, R₃, R₄, R₇, and R₈. When V⁺_O4=|V^­_O4|, the tolerance is symmetrical. With the given values, the output state changes when one input signal is approximately 30% higher than the other. If you need to use the circuit over a wide temperature range, you should take the thermal dependence of the threshold levels into consideration. The circuit uses an LM324 quad op amp. If you use a rail-to-rail amplifier (for example, the LMC6484), the output limiter is unnecessary. (DI #2166)

Simple LCD interface takes two wires

Ed Maste, Jem Designs, Pickering, ON, Canada

Alphanumeric LCD modules can provide an attractive display for a project, but their parallel I/O lines require a large number of outputs from a µC. For example, a direct LCD interface would consume all of the I/O pins of a small µC, such as the eight-pin PIC12C508 from Microchip Technology (Chandler, AZ).

However, the circuit in Figure 1a implements a clocked serial input for an LCD module and allows a µC to communicate with the LCD over just two signal lines. You can fit the circuit onto a small pc board and mount the board directly behind the LCD module. The connection between the board and LCD module comprises just four wires, including V_CC and ground.

A 74LS164 serial-to-parallel shift register forms the heart of the circuit and communicates with the LCD module in 4-bit mode. The shift register's outputs directly drive the LCD module's data inputs, DB7 through DB4, as well as RS, the control/data select input. The only signal that is not a direct output from the shift register is the LCD module's enable pin, which is Pin 6. R₄ and D₁ derive the enable input and ensure that the enable signal remains low until valid data is present at all other outputs. R₁ is a current-limiting resistor for an LED backlight if the LCD module has one, and R₂ and R₃ set the contrast level of the module. You can replace R₂ and R₃ with a potentiometer if an adjustable contrast level is desirable.

The µC must first clock in at least seven zeros for the first write (Figure 1b). This series of zeros guarantees that output Q_G of IC₁ is low and will remain so for the next six clock cycles. This low level ensures that the enable input (Pin 6 of the LCD module) remains low because of diode D₁. The serial-input stream then must consist of a one, followed by RS, and finally DB₇ through DB₄. With the data input low, an additional clock pulse shifts in a zero and lines up all of the outputs to the LCD module with the correct shift-register pins. The first clocked-in one now appears at Q_G, which reverse-biases D₁. The enable continues to remain low because the data input to the circuit is low, and this situation pulls the enable low through R₄. The data input then must go high for at least 450 nsec without a clock pulse to provide the enable pulse for the LCD module. This process, including clocking in at least six zeros, is then repeated for the next 4-bit write.

For further information, including minimum cycle times and 4-bit-mode communication, consult the technical documentation provided by an LCD module manufacturer, such as Optrex (Plymouth, MI). (DI #2177)

Inexpensive logic controls stepper motor

David Ellis, Ellis Lindauer, Pullman, WA

A number of sophisticated ICs for stepper-motor control are now available. However, the advanced features of these chips--self-clocking, high-current drive, and full-step, half-step, and direction control--are often unnecessary or remain unused. For a design that needs to control only the number of steps, drive speed, and direction, you can make a very simple and inexpensive driver using two low-level logic chips (Figure 1). The cost of this controller is less than $1; the cost of dedicated motor-control ICs starts at around $5. The drawback is a slight increase in board space.

Going back to the basics, you can control a standard stepper-motor drive, whether bipolar or unipolar, using a four-step sequence (Table 1a). By replacing the on and off states with ones and zeros, respectively (Table 1b), Column B becomes the logical inverse of Column A, and Column D becomes the logical inverse of Column C. Thus, the corresponding state diagram (Figure 2) comprises just 2 bits. Clockwise rotation results from using a logical one to move sequentially from state one to state four and back to state one. Likewise, counterclockwise rotation results from using a logical zero to move through the states in the reverse order.

You can then produce the present-state/next-state assignment (Table 2) and the next-state maps (Figure 3). Then, by inspection, the logical choice is to loop the state maps out for D flip-flops, which produces the following two logic equations:

DA=((DIR)(C))+((DIR) (C));
DB=((DIR) (A))+((DIR) (A)).

Equation 1 is an exclusive NOR, and Equation 2 is an exclusive OR. To save space, you can use a single quad XOR chip to implement both equations. A dual D flip-flop completes the logic driver, as Figure 1 shows. Using rising-edge-triggered D flip-flops helps keep the  design simple while eliminating mode-change faults.

The circuit derives the four outputs from the Q and Q outputs of D flip-flops IC_2A and IC_2B in Figure 1. IC_1A XORs the Q output of flip-flop IC_2B with the DIR input, and the circuit transforms the output into an XNOR by using IC_1B as a controlled inverter. IC_1B then drives the D input of flip-flop IC_2A. Similarly, IC_1C XORs the Q output of IC_2A with the DIR input. The output of IC_1C drives XOR IC_1D, which acts as a noninverting buffer. The output of IC_1D drives the D input of IC_2B. Using XOR gate IC_1D as a buffer keeps the propagation delays to the D inputs of the flip-flops equal, which helps the circuit avoid any race conditions. The STEP signal is the step-rate input, which drives the clock inputs of both flip-flops.

The last design task is to add the appropriate-sized transistors to drive the stepper motor. In the case of the unipolar motor, output signals A, B, C, and D can   directly drive the transistors. To drive a bipolar motor, you can use the A and C outputs to drive one-half of two H-bridges and the B and D outputs to drive the other corresponding half of the H-bridges. This design is possible because the B output is the inverse of A, and D is the inverse of C. (DI #2176)

Low-voltage reset operates below 2.7V

Bob Kelly, Maxim Integrated Products, Sunnyvale, CA

New personal digital assistants, pagers, and other battery-powered systems operate at or below 2.7V, but power-on resets with thresholds below 2.6V are not commonly available. You can resolve this problem using a circuit that combines a 1.2V reference and a micropower regulator (Figure 1a). IC₁ integrates these two functions in a tiny SOT-143 package. A power-on-reset function must become active before the supply voltage reaches its nominal value, and IC₁ operates properly for supply voltages above 1.21V.

The R₁/R₂ divider and internal 1.204V reference establish a threshold that determines when the circuit asserts an active-low at the output. For the values in the figure, this threshold is 2.25V (Figure 1b). IC₁ has an open-drain output, so R₃ and C₁ control the length of the active-low pulse, RESET. In this case, the pulse length, or reset interval, is approximately 54 msec, which is sufficient reset time for most µCs and other digital circuits.

Low power consumption distinguishes this circuit. The IC typically draws only 5 µA, and the R₁/R₂ divider draws slightly more than 1 µA in a 2.7V application. Pullup resistor R₃ consumes power only when the supply voltage droops out of tolerance, so the power loss is minimal in normal operation.

To prevent erratic behavior, IC₁ offers approximately 6 mV of built-in hysteresis. For more hysteresis, you can add a large-value resistor, R_HYST, between the IC's input and output; to reject short transients, IC₁ has an inherent glitch immunity of 35 µsec with 100 mV of overdrive. The input capacitance works with R₁ and R₂ to provide some lowpass-filter action. For further immunity from transients, which is unnecessary unless the power bus is noisy, you can form an additional lowpass filter by adding a small-value capacitor, C_G, to the input pin. (DI #2174)

Alternating LED blinker uses four parts

Andy Meng, Cincinnati, OH

The circuit in Figure 1 is an easy-to-make attention-getter and runs for a week or longer on two AA cells. In September, I used this circuit for a school fundraiser, and it helped me generate more than $100. My dad showed me a circuit in EDN that did the same thing, but it uses more parts (see "Alternating LED flasher uses minimal parts," EDN, Nov 20, 1997, pg 104).

The main element of this circuit is LED₁, a Radio Shack 276-036 blinking red LED. D₁ can be almost any silicon diode. The forward bias of D₁ brings the turn-on voltage of LED₂ up to 2.5V. R₁ is a current-limit resistor for LED₁, and this resistor also reduces the current of LED₁ for longer battery life.

LED₂ is a Radio Shack 276-041 red LED. When you apply power, LED₁ turns on and drops the voltage across LED₂ to 1V. When LED₁ turns off, the voltage across LED₂ equals 3V, and LED₂ turns on. (DI #2172)

Spice generates PSK and FSK signals

Debra Horvitz, Galahad Systems, Laguna Hills, CA

Creating generators for amplitude-,  frequency-, and phase-modulated signals can greatly simplify communication-system simulation. Although Spice includes a basic set of waveform generators, it includes no built-in support for many types of signals. You must create these signals from combinations of elements, and you can create variations of these built-in generators using Spice 2- dependent sources. However, using dependent sources to generate complex waveforms can require fairly complex Spice subcircuits.

Fortunately, the nonlinear, arbitrary dependent source--the B element--in Berkeley Spice 3 and IsSpice4 (Intusoft, San Pedro, CA) provides a quantum leap in capability over Spice 2-dependent sources. The B element is more versatile and easier to use. For example, Listing 1 is the IsSpice4 subcircuit for a parameterized phase-shift-keying (PSK) source; Listing 2 is the subcircuit of a parameterized frequency-shift-keying (FSK) source. Figure 1 shows the resultant output signals of each subcircuit generator.

The PSK subcircuit produces a coherent binary PSK signal according to the following equations:

where EB is the transmitted energy per bit, TB is the bit duration, and f is the transmission frequency equal to NC/TB. (NC is an integer constant, and the period is 2×TB; thus, the duty cycle equals 50%.) In Listing 1, the input voltage source, VSIG, produces the polar form of the input signal. Using the B1 element, the subcircuit  multiplies this input by the local oscillator voltage,    VLO1, to produce the PSK output signal.

The subcircuit, FSK, produces a coherent binary FSK signal according to the following equations:

where f₁ is the high-bit transmission frequency, and f₂ is the low-bit transmission frequency. The frequency, f₁, is equal to NC+1/TB. The frequency, f₂, is equal to NC+2/TB. For simplicity, two pulse generators, VSIG and VSIGN, produce the input signal, m(t), and the inverse of the message signal, M(t), respectively. Again, using the B1 element, the subcircuit code multiplies these signals by the appropriate frequency generator: VLO1 for logic high and VLO2 for logic low. The sum of the resultant signals produces the FSK output signal. (DI #2173)

Frequency multiplier improves line readings

Yongping Xia, Teldata Inc, Los Angeles, CA

Because of the low frequencies involved, accurately measuring line-frequency variations is complicated. When you use an ordinary frequency counter with a 1-sec gate time, the reading would be 59, 60, or 61 Hz. To obtain 0.01-Hz accuracy, you must increase the gate time to 100 sec, a scale that most frequency counters do not offer. Moreover, reading updates are slow with this scale choice. One way to improve reading accuracy without sacrificing update time is to use a frequency multiplier. For instance, a frequency counter with a 1-sec gate time could provide 0.01-Hz accuracy if you multiply the line frequency by 100. Traditionally, you would configure the multiplier by using a VCO, a PLL, a frequency divider, and a lowpass filter. Figure 1 shows another method, using only one component, to multiply the line frequency.

The PIC12C508 is an eight-pin, low-cost µC. It has a built-in 4-MHz oscillator and a reset circuit; it thus needs no external components. One of the µC's unique features is its software-based clock-frequency calibration. The controller dedicates one register, OSCCAL, to the calibration function. The upper 4 bits of OSCCAL accommodate 16 steps of calibration. Each step changes the clock frequency approximately 1.6%. The maximum change is approximately 25%. The line signal routes to the µC's GP3 pin. When the controller detects a low-to-high change in GP3, the program generates 100 pulses on GP5 and ignores the condition of GP3 (Listing 1). It then rechecks the status of GP3. A high value for GP3  means that the pulse generation is too slow; OSCCAL then increases by one step. If GP3 is low, then a counter operates until GP3 goes high.

The number in the counter represents the delay (t_W) between the last pulse and the next line-signal change. The µC compares t_W with a fixed number. If t_W is larger than that number, indicating that the clock frequency is too high, the value in OSCCAL decreases by one step to slow down. If t_W is smaller than the fixed number, the value in OSCCAL increases by one step to speed up. Thus, the automatic clock-frequency adjustment continuously sends a signal at 100 times the line frequency. Note that, because of the calibration range, this approach has a limited input-frequency range. However, it accommodates line-frequency measurements from 58 to 62 Hz. You can download the assembly code from EDN's Web site, by clicking here: download. (DI #2182)

Circular slide rule provides quick results

Jacek Pawlowski, PW INMEL, Zielona Góra, Poland

In analog-circuit design, most calculations you make need not be very precise. If you need an LED-current calculation or a coupling-capacitor value, for example, ±5% or even ±10% accuracy is usually adequate. It's sometimes inconvenient to make these calculations with a pocket calculator. For example, finding the cutoff frequency of a 3.3-kiloohms/47-pF network requires approximately 20 key presses. The circular slide rule using the patterns in Figures 1 through 4 simplifies such calculations. The slide rule uses one large, opaque, double-sided wheel and two smaller, transparent wheels.

You can make the opaque wheel by gluing back-to-back the patterns in Figures 2 and 4. For the transparent wheels, you simply photocopy the patterns in Figures 1 and 3 onto overhead-transparency foils. To attach the wheels, you can use a rivet or a screw and nut. Using side A (Figures 1 and 2), you can calculate resistance (V/I), power (VI), and percentage products       (greek delta,uc=greek delta,lc·X, where greek delta,lc is a percentage). X can be voltage, current, power, or resistance. Side A also gives standard EIA values for resistance.

On side B (Figures 3 and 4), you can calculate the  following formulas:

Any quantity can be the unknown. For example, you can calculate

You can modify the slide rule to incorporate the formulas you use most often. The design of the slide rule uses AutoCAD LT. (DI #2137)

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