March 26, 1998

WHAT'S HOT IN THE DESIGN COMMUNITY

New DSP architecture highlights atomic read-modify-write and real-time emulation

TI has once again expanded its fixed-point DSP architectures with the introduction of the TMS320C27xx. The C27xx represents the evolution of the TMS320C2xx toward more µC functionality, C-compiler friendliness, and debugging capabilities. Although the C27xx's register set is compatible with the C2xx, the instruction set and pipeline functionality differ. This accumulator-based architecture has an eight-phase pipeline, implying that eight instructions can be active at once. During the first phase, the CPU fetches either one 32-bit instruction or two 16-bit instructions from program memory. Because not all reads and writes happen in the same phases of the pipeline, TI engineers designed in an atomic read-modify-write capability in a pipeline-protection mechanism that stalls instructions as needed to ensure that reads and writes to the same location happen in the correct order. The control logic pumps in inactive cycles between instructions that would cause the conflicts. You can reduce these types of pipeline-protection cycles if you insert other instructions in your program between the conflicting instructions.

The main functional units attached to the pipeline include the program-control logic, program-address-generation logic with a 22-bit program counter, an address-register arithmetic unit, a 32-bit ALU, a 16×16-bit single-cycle multiplier and multiply-accumulate unit, and a 32-bit barrel shifter. An instruction queue within the program-control logic comprises enough registers to hold four 32-bit or eight 16-bit instructions. The C27xx supports a mixture of 16- and 32-bit instructions, but most instructions are 16 bits. The C27xx implements a modified Harvard architecture and uses separate 32-bit on-chip read and write buses that can each fetch or store two words per cycle. The device also includes a 32-bit program bus. Besides supporting the standard DSP addressing modes, the C27xx supports a circular buffer but has no hardware support for bit-reversed addressing.

TI offers a C compiler, an instruction-set simulator, a debugger, evaluation modules, and simulation models for ASIC design. TI also provides a code-translation tool that allows you to translate C2xx into C27xx code. The C27xx contains a JTAG-emulation module that is new for TI's DSPs. On-chip emulation logic supports a debug-and-test DMA unit, a data-logging utility, a 32-bit counter for performance benchmarking, multiple debugging events, real-time-mode operation, and interrupt-generation capabilities. The DMA unit allows the emulator to access registers and memory during unused instruction cycles without CPU intervention. Using the real-time operating mode, you can halt the main body of code (that is, reaching a breakpoint), but the CPU still services interrupts. You can even break within one interrupt and still service others.

TI combined this JTAG-emulation module with its Real-Time-Data-Exchange (RTDX) capability. RTDX allows the TMS320C27xx to export data at 8 kbytes/sec. In a motor-control application, for example, RTDX allows you to modify registers and instructions, stream data variables, or set and execute hardware breakpoints without affecting the motor's operation. RTDX communicates between the host computer and the DSP target using an emulator and a procedural library; this internal data-exchange library uses the scan-based emulator to move data on and off chip via the JTAG interface.

--by Markus Levy

Texas Instruments Inc, Dallas, TX. 1-800-477-8924, ext 3555, www.ti.com.

Floating power manager frees you from ground's constraints

Hot-swap capability is important for PC cards in many low-voltage systems, and you can find numerous ICs that manage the power rails. But it's more difficult when the voltages go beyond 3, 5, or 12V, such as in communications and data-processing systems. Unitrode's UCC3917 positive-voltage hot-swap manager avoids these voltage difficulties by floating, so that its only limits on operating voltage are the ratings of any external components, not the IC itself. The IC derives its own supply from an internal charge pump, which operates from V_OUT; the charge pump derives its power from an internal 5V shunt regulator, so the output load provides I_DD.

This 16-lead IC sets and monitors the fault current level, maximum output source current, maximum fault time, soft-start time, and average n-channel MOSFET power limiting. You set desired limits and thresholds via passive components and voltages. The device also includes a fault output that signals if its ability to shut off the output MOSFET has been compromised, which could be catastrophic. The IC, which is available in DIP and SOIC packages, costs $1.54 (1000).

--by Bill Schweber

Unitrode Corp, Merrimack, NH. 1-613-424-2410, fax 1-603-429-8963, www.unitrode.com.

1-Gbit Ethernet switch chips incorporate layers 2 and 3

PMC-Sierra's new three-chip Elan-Exact Gigabit Ethernet switch set for LAN switching applications includes the Eagle, Felix, and Encore chips. The Eagle chip contains a Gigabit Ethernet port controller, the Felix chip contains eight 10/100-Mbit Ethernet port controllers, and the Encore switch-matrix-controller chip provides a switching backplane that can achieve an aggregate bandwidth of 16 to 32 Gbps. The chips provide stackable and modular switches over a range of port counts and configurations.

Both the Felix and the Eagle use the SmartPath embedded RISC core, which provides the Layer 2 bridging and Layer 3 routing, and the Exact bus. The port controllers can connect to one other controller or to the Encore switch-matrix when more than two port controllers comprise a switch through the Exact bus. This architecture lets you incorporate proprietary features, such as video LANs, policy-based priorities, or extensive security, by employing the SmartPath RISC core, external µPs, or ASICs. The Elan-Exact chip set delivers nonblocking, wire-speed, low-latency switching for as many as 128 ports of 10/100-Mbit or 16 ports of  Gigabit Ethernet. It also lets you attach synchronous- optical-network, T3, or T1 point-to-point protocol devices.

Samples of the Elan-Exact chip set will be available this quarter. All three devices come in 352-pin BGA packages. The PM3370 Elan-Eagle and PM3380 Elan-Felix cost $159 (1000) each, and the PM3390 Elan-Encore costs $129 (1000).

--by Stephen Kempainen

PMC-Sierra, Vancouver, BC, Canada. 1-604-415-6000, fax 1-604- 415-6200, www.pmc-sierra.com.

New EDA tool kit boosts CDMA design

Two products from Cadence, the new EnWave CDMA Tool-kit and an enhanced version of the Visual Architect behavioral compiler, can help you with your code-division multiple-access (CDMA) chip designs. Designers employ CDMA chips in many types of communication systems, including satellite, cellular telephone, and wireless local loop.

You use the CDMA Toolkit during the top-level portion of a design for exploring system configurations. The tool kit has a library of floating-point algorithmic blocks that you graphically configure into a system testbench. The testbench represents an executable model of the physical layer of the CDMA system, along with the signal-propagation environment in which the system will operate. A designer works with this model to explore design functionality and perform-ance, optimizing the design along the way.

After you choose the desired system architecture, you use the tool kit's fixed-point algorithmic-block library to model portions of the system that you will implement in hardware. You simulate these blocks within the floating-point system testbench. With the fixed-point models, you also optimize the system's datapath for system-parameter trade-offs, such as cost, signal quality, and power dissipation. To assist you with this optimization, the CDMA Toolkit includes blocks for quantifying performance metrics, such as signal-to-quantization noise ratio and bit-error-rate.

After optimizing your fixed-point model, you can generate a behavioral HDL description representing the design. Visual Architect, which Cadence enhanced to accommodate multirate design, generates RTL HDL from the behavioral code. You then use the RTL code with logic synthesis and other tools to develop your system hardware.

Both the CDMA Toolkit and Visual Architect run on Unix-based platforms. Tool prices start at $20,000 for the tool kit and $70,000 for Visual Architect.

--by Jim Lipman

Cadence Design Systems, San Jose, CA. 1-408-943-1234, fax 1-408-943-0513, www.cadence.com.

Low-density flash memory targets EEPROM

Integrated Silicon Solution Inc's (ISSI's) flash-memory division--formerly, an independent company called Nexcom Technology--has expanded its Serial Flash product line downward in density with 1- and 4-Mbit versions. The devices come in 8×13-mm TSOPs and 15×45-mm removable modules; offer 16-MHz, four-pin SPI and proprietary two-pin interfaces; and operate at 3 and 5V. 

Typical read and write current draw is less than 5 mA at 3V with less than 1 µA of standby current. Erase block sizes of 264 bytes match those of Atmel's (www.atmel.com) Serial Data-Flash memories and simplify EE-PROM replacement. Two on-chip page buffers improve block-rewrite speeds, which are less than 5 msec and include both automated erasing and reprogramming operations.

The 1-and 4-Mbit devices cost $3.45 and $6.56 (10,000), respectively. Corresponding module prices are $4.72 and $7.87. ISSI also offers a $149 evaluation board and free reference EEPROM-emulation and file-system software.

--by Brian Dipert

Integrated Silicon Solution Inc, Santa Clara, CA. 1-408-588-0800, fax 1-408-588-0805, www.issiusa.com.

Ultrathin touchpad has pen input, mouse functionality

A 0.027-in.-thick touchpad from Interlink Electronics provides both pen input and mouse control. The VersaPad's pen-input capability is WinTab-interface compatible. The touchpad is available in 25.5×25.5 mm for cell phones and two-way pagers and 55.5×39.5 mm (active area) for notebook PCs and keyboards. The VersaPad is scalable for any custom pad size. The input device supports both fingertip and stylus input modes, with optional touchpad resolution of 1000 lines per axis.

Hardware interfaces for the VersaPad include PS/2, RS-232C, and user-defined custom interfaces. Current consumption is 2 to 5 mA during operation, dropping to 0.1 µA at rest. The touchpad resists moisture, harsh chemicals, ESD, and EMI. Its tested lifetime is 5 million strokes (118 miles). To assist you in evaluating the VersaPad, Interlink offers an OEM sample kit that co  ntains everything you need to test and integrate the device. The kit costs $150 plus shipping.

--by Bill Travis

Interlink Electronics Inc, Camarillo, CA. 1-805-484-8855, fax 1- 805-484-8989, www.interlinkelec.com.

Debugging tools combine logic analysis, emulation

By putting the same debugging tools in the hands of hardware and software engineers, Hewlett-Packard has taken a major step toward eliminating the finger-pointing that occurs during the integration of a new µP-based system. Traditionally, hardware engineers rely on logic analyzers to evaluate the performance of their designs, and software designers favor in-circuit emulators to study code execution. HP's 16600/16700 series logic-analysis systems integrate processor emulation, software analysis, signal measurement, and pattern generation. According to HP, hardware designers can use scope- or timing-analyzer functions to view analog signals and timing relationships, and embedded-software developers can control processor execution, read registers, single-step, or set breakpoints. By employing the same tools, users can easily duplicate and communicate integration problems to other design-team members for isolation and correction.

Both logic-analysis systems provide a graphical, X-windows interface to set up measurements and display multiple time-correlated  views of system characteristics. For µPs with on-chip emulation, you can install an emulator module to connect the µP debugging resources to the logic analyzer. For µPs without on-chip emulation, analysis probes capture bus activity for source-code display by inverse-assembly tools. Both systems accept most of the measurement modules from the HP 16500C logic-analysis system and emulate the MPC 500/800, PowerPC 600/700, Pentium, Pentium Pro, CPU-32, ARM, M.CORE, NEC V83X, and Hitachi SH3/SH4 µP families. Analysis probes are available for 150 additional µPs and buses.

The $9900 HP 16700A is an expandable mainframe with five slots for measurement modules and two slots for emulation modules. The $5000 HP 16701A expansion mainframe doubles the slot count for large systems. The HP 16600 series is a preconfigured logic- analysis system with one measurement slot, one emulation slot, and as many as 204 state/timing channels. Prices for the HP 16600 series start at $10,040 for the 68-channel 16603A. Prices of emulation probes and modules start at $2995.

--by Warren Webb

Hewlett-Packard Co, Palo Alto, CA. 1-800-452-4844, ext 5645, www.hp.com/go/logicanalyzer.

Budding FPGAs beat last year's crop

With the arrival of a new season, programmable-logic architectures are springing up in abundance. Each shares a common feature-set foundation with their predecessors and improve on their manufacturers' previous state of the art in both subtle and obvious ways.

Altera is moving its Flex10K architecture to a 0.25-µm, five-layer-metal process in a two-phase approach. The Flex10K "E" family goes a step beyond the EPF10K100B and improves the embedded-array-block (EAB) structure (see "Programmable-logic heavyweights pack a punch," EDN Nov 20, 1997, pg 18). Doubling each EAB's density from 2 to 4 kbits, bus width from 8 to 16 bits, and number of I/O ports from one to two enables more efficient and higher performance FIFO and dual-port SRAM configurations. (Internet newsgroup comp.arch.fpga had criticized previous Flex10K devices for these oversights.) Altera predicts that the EPF10K100E, scheduled for sampling during the fourth quarter, will cost $30 (50,000) by the end of 1999.

DynaChip has migrated its DL5000 FPGAs, built on an IBM (www.ibm.com) 0.8-µm BiCMOS process, to a 0.35-µm CMOS process at Taiwan Semiconductor Manufacturing Co (www.tsmc.com.tw). The result, the DL6000 family, offers slightly lower performance than the previous generation but delivers more than enough speed for most programmable-logic designs. The DL6000 family also retains the vendor's unique active-repeater architecture for reduced routing delays (see "Heat is on for speed-limit-breaking FPGA architecture," EDN, July 17, 1997, pg 24). Other upsides to the process conversion include lower cost per gate, higher gate counts per device, multiple clock trees, two on-chip PLLs, and 32 bits of SRAM per logic block for 100-MHz, 32-bit×32 FIFO buffers and other embedded-memory configurations. The lowest speed DL6009 costs $60 (1000), and the DL6035 costs $202 (1000). Performance improves roughly 10% with each higher speed grade, according to the vendor, with a corresponding price increase of 25%.

Lucent Technologies' 5V OR3C and 3.3V OR3T ORCA devices, which the company announced two years ago, are available for sampling. Doubling the number of look-up tables per logic block from four to eight and increasing the intrablock routing reduce the reliance on slower global interconnection. This architecture change, along with additional dedicated memory-control signals, quadruples the amount of RAM per logic block in dual-port configurations (Table 1). Two programmable clock managers find use as either PLLs or delay-lock loops, and the ability to dynamically reconfigure their parameters while leaving the remainder of the device untouched opens the door to some interesting power-management techniques. Supplemental logic and interconnect cells (SLICs) in each logic block enable fast decoding of wide, combinatorial-logic functions, a task that PALs or CPLDs previously accomplished best. Back-end place-and-route support comes from Lucent's ORCA Foundry Version 9.2 software. The OR3T55-5 will cost $71.90 (25,000) in the fourth quarter.

--by Brian Dipert

Altera Corp, San Jose, CA. 1-408-894-7000, fax 1-408-435-1394, www.altera.com.

DynaChip Corp, Sunnyvale, CA. 1-408-481-3100, fax 1-408-481-3136, www.dyna.com.

Lucent Technologies, Allentown, PA. 1-610-712-4331, fax 1-610-712-4209, www.lucent.com.

Logic-synthesis tool goes triple speed

The latest version of BuildGates, Ambit's logic-synthesis tool, runs as much as three times faster than its predecessor, according to the company. The new version also adds intellectual-property (IP) integration, dual-language (VHDL and Verilog) compilation, and timing verification with DCL (delay-calculation language).

BuildGates supports "gray-box" modeling, which lets you view the timing of an embedded core while protecting the inherent IP of that core. Many core models are "black boxes," which limit access to the core's internal timing to protect the core's proprietary design features. The lack of information about the core's internal timing limits your ability to optimize chip performance and may result in inaccurate core timing models. Gray-box modeling lets you design chips containing embedded complex cores, such as µPs, with higher performance than black-box core models can achieve. By supporting DCL timing standards, which are gaining wide acceptance with ASIC companies, BuildGates also gives designers better correlation with ASIC-vendor timing numbers.

Another useful BuildGates feature is NaviGates, software that links design views and combines design-hierarchy navigation, block and schematic viewing, and improved reporting of synthesis results. NaviGates features fan-in/fan-out viewing, the ability to traverse a design's connectivity, and enhanced schematic-information display. BuildGates runs on Unix platforms and has a starting price of $98,000.

In a related development, Synopsys has announced that many of its EDA products, including the Design Compiler logic-synthesis tool, will be available for Windows NT by the end of this year. Prices for the Windows-based tools will be the same as for their Unix-based counterparts. Other Synopsys tools that the company plans to port to Windows NT platforms by year-end include the Chronologic VCS Verilog simulator, Behavioral Compiler, and the DesignWare functional-core family.

-- by Jim Lipman

Ambit Design Systems, Santa Clara, CA. 1-408-566-8000, fax 1-408-566-8001, www.ambit.com.

Synopsys, Mountain View, CA. 1-650-962-5000, fax 1-650-965-8637, www.synopsys.com.

Speedy programmable-logic tools improve designs

QuickLogic and Xilinx have improved the performance of their design-tool packages. QuickLogic's QuickWorks Version 7.0 FPGA-design-tool suite combines with a higher speed version of the company's pASIC 3 family to improve device speed 25 to 50% over devices designed with the previous version of QuickWorks. Another enhancement of the design-tool suite is a new interface that lets you enter design constraints for a chip or portions of the chip. You specify parameters such as multiple clock frequencies, clock-to-output delays, and setup times. An integrated synthesis tool from Synplicity (www.synplicity.com) interprets these constraints and determines the optimal number of logic levels your design needs. QuickWork's mapper uses these synthesis results to place timing-critical signals into high-speed paths on the chip, which results in a faster overall chip. The design-tool suite also includes a Verilog simulator, which lets you evaluate the timing of your design before physical layout.

QuickWorks costs $2995 and runs under Windows. A starter system, QuickTools Plus, includes schematic-entry, place-and-route, and static-timing-analysis tools but lacks an HDL-based design capability. QuickTools Plus costs $495 for Windows and $1995 for Unix.

Xilinx has also upgraded its design tools with a faster and more efficient version, Alliance Series 1.4. New Alliance place-and-route algorithms let you design your chip in less time than with previous versions. It also includes a graphical place-and-route option that lets you choose a place-and-route level anywhere between minimum runtime and best placed-and-routed chip results.

Alliance now includes behavioral-level Unified Simulation libraries that let you simulate behavioral code throughout the design cycle. These new libraries complement Xilinx's VHDL and Verilog timing-simulation libraries. Alliance also includes the free Turns Engine tool, which lets you make multiple place-and-route runs per design across a network of Unix workstations. This networked multiple-run capability helps you optimize design performance without adding the runtime that a single platform performing placement and routing would require. Alliance supports all Xilinx FPGA and CPLD families and is available for both Windows and Unix platforms. Prices start at $495 for Windows operation and $795 for a Unix version.

--by Jim Lipman

QuickLogic, Sunnyvale, CA. 1-408-990-4000, fax 1-408-990-4040, www.quicklogic.com.

Xilinx, San Jose, CA. 1-408-559-7778, fax 1-408-559-4114, www.xilinx.com.

Three functions in one IC meet many mundane interface needs

Applications such as zero-crossing detectors, photodiode preamp interfaces, and sensor signal detection often need a basic op amp to boost signal levels, followed by a comparator and its reference to validate signal state. Maxim's MAX9000 family, comprising six slightly different members, simplifies the task by putting the three functions into one package as small as an eight-lead device, depending on the model. You can choose among combinations of op-amp gain stability (1 or 10V/V) and gain bandwidth (1.25 or 8 MHz), as well as availability of a shutdown mode that drops the operating current from 500 to 2 µA.

Depending on the model, the reference output internally connects or does not connect to the comparator's inverting input. The 1.23V ±1% bandgap reference can source or sink as much as 1 mA and tolerate 100-nF loads. Op-amp outputs are stable with loads as high as 250 pF, and the outputs of the op amp and comparator can swing rail-to-rail while supplying currents as high as ±2.5 and ±4 mA, respectively. The devices, which cost $1 to $2 (1000), are designed with 2 mV of comparator hysteresis to provide noise immunity and prevent oscillation, even with slow inputs.

--by Bill Schweber

Maxim Integrated Products, Sunnyvale, CA. 1-408-737-7600, fax 1-408-737-7194, www.maxim-ic.com.

Novel RF packaging cuts cost, boosts performance

A new packaging technology from Mini-Circuits reduces size and cost and improves performance for RF components, such as mixers, splitters, couplers, and transformers. The package has a profile as low as 0.078 in. high and preserves the same footprint as other components. In conventional packages (Figure 1a), a bottom pc board mounts parts and makes internal connections. With the new technique (Figure 1b), the circuit mounts inside the cover. Terminations attach to the top of the case, and welded connections are close to the package leads.

The result is improved in high-frequency performance because of the shorter connections. Turning the module upside down provides coplanarity with connections on the customer's board. The absence of a bottom supporting plate provides the space necessary to allow an aqueous wash to drain thoroughly. The package leads have solder plating, and the package has a flat surface for high-speed pick-and-place operations. Tape-and-reel packaging is available.

--by Bill Travis

Mini-Circuits, Brooklyn, NY. 1-718-934-4500, fax 1-718-332-4661, www.minicircuits.com.

Figure 1

The RF packaging technique in (b), developed by Mini-Circuits, cuts costs and boosts performance, compared with the conventional packaging method in (a).

Optical transceivers support increased port density

Several fiber-optic-component vendors are employing the new MT-RJ modular cabling system, which brings many of the benefits of the RJ-45 modular plug-and-jack system to fiber optics. Network switch and router systems use the small-form-factor transceivers to increase port density, which lowers the overall per-port system cost. The MT-RJ transceiver is about half the size of the standard SC fiber- based transceiver, allowing designers to double the port density. The MT-RJ system supports single-mode and multimode fiber applications.

The first 1300-nm, LED-based MT-RJ transceivers come from Hewlett-Packard. They support Fast Ethernet, asynchronous-transfer-mode OC-3, and fiber-distributed data- interface applications. The transceivers use a 3.3V power supply, halving the power consumption and board space. Devices for Gigabit Ethernet and Fibre Channel should be available in the second half of this year. Samples of the 125- and 155-Mbps MT-RJ transceivers are available and cost less than $40 (10,000).

--by Stephen Kempainen

Hewlett-Packard, Palo Alto, CA. www.hp.com/go/fiber.

Dual-axis, 2g accelerometer helps you deal with jerks and more

Say "accelerometer," and you naturally think of measuring displacement, velocity, acceleration, or "jerk" (the rate of change of acceleration). However, an accurate, low-cost, 2g accelerometer, such as the ADXL202 from Analog Devices, lets you also measure parameters such as inclination (tilt) due to the static acceleration resulting from the ubiquitous force of gravity. These abilities open opportunities in applications that benefit from unconventional approaches to sensing, such as handheld game controllers, head-mounted controls, field instrumentation, safety tilt monitors, and package-shipment monitors. This silicon micromachined device costs $9.95 (10,000) and comes in a standard 14-lead surface-mount package. It provides PWM outputs that interface directly to a microcontroller without glue logic and also offers a filtered analog output.

The sensing element is a single, relatively large, floating proof mass that is tethered at its corners to the larger silicon die. As static or dynamic acceleration causes the mass to move in its plane, a pair of independent capacitance transducers along the edges of the mass resolve this motion into the x and y directions. The accelerometer then conditions, amplifies, and converts the analog signal from each axis to a PWM output signal for system use. Note that micromachining also means micro values at the die level:  The smallest detectable capacitance change in this circuit is 20 zF (1 zeptofarad = 10^­21F), resulting from the 1.3-mm gap between capacitor plates, and the full-scale capacitance change is 10 fF.

Resolution is 5 mg at 60-Hz bandwidth with a noise floor of 500 mV/ˆHz. The ±2g sensor has typical linearity of 0.2% of full scale, operates from a 2.7 to 5.25V supply, and requires less than 0.6 mA of current. The only external components it requires are a pair of analog filtering capacitors--one per axis--plus a resistor to set the duty cycle. Two hardware-evaluation tools are available: a demonstration board with an RS-232C interface and PC software that performs data logging, as well as a prototyping board. To further aid designers in trading off among device parameters, such as supply voltage, signal bandwidth, resolution, peak-to-peak noise, and PWM output range, the vendor also provides an interactive Excel spreadsheet via the Internet.

--by Bill Schweber

Analog Devices Inc, Norwood, MA. 1-781-937-1428, fax 1-617-761-7607, www.analog.com.

Desktop drive hurdles 11.5-Gbyte capacity mark

Seemingly on a never-ending growth path, disk drives are moving to 11.5-Gbyte capacity at the high end of PC product families. With its DiamondMax 2880, available now, Maxtor claims it is the first to ship 11.5-Gbyte drives in high volumes. The drive features a 5400-rpm spindle, 9-msec average seek time, and 33-Mbyte/sec UltraDMA transfer rate. The drive carries a three-year warranty and MTBF rating of 500,000 hours. Maxtor expects the drive to cost approximately $479 at retail.

--by Maury Wright

Maxtor Corp, Milpitas, CA. 1-800-262-9867, www.maxtor.com.

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