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March
26, 1998
Cover Story
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High-speed datapaths bypass bus bottlenecks
Today's standard backplane bus systems offer low-cost, off-the-shelf hardware and
design flexibility but have severe bandwidth limitations. To increase data rates and
retain the advantages of the bus system, designers are bypassing the bus and directly
transferring data between subsystems.
--Warren Webb, Technical Editor
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Design Features
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Chip place-and-route tools lay it on the line
The final step in ASIC implementation is defining your chip's physical layout. With
interconnect-dominated deep-submicron designs, the tools and techniques you use determine
whether your design is successful.
--Jim Lipman, Technical Editor
Product Preview: The Embedded
Systems Conference
Plenty of new products will be on display at the upcoming Embedded Systems Conference,
which runs from March 31 to April 2 in Chicago.
Use logic-analyzer setup/hold triggering to
ensure timing margins
With a logic analyzer that offers setup/hold triggering, you can easily measure system
timing margins. Straightforward examples explain how to do it.
--Colin L Shepard, Tektronix Inc
Electromigration wreaks havoc on IC design
Current IC-design practices make perfect conditions for electromigration, which causes
broken connections. A thorough understanding of the problem and its prevention help
prolong an IC's life.
--Jim Lloyd and David Overhauser, Simplex Solutions Inc
The right motor can position your application
for success
To design a product that uses motors for position control, you should understand the
strengths and weaknesses of several motor types. Then you can choose the best motor or
motors and begin selecting or designing a suitable controller.
--Chuck Lewin, Performance Motion Devices Inc
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Leading Edge
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