March 26, 1998

Cover Story

• High-speed datapaths bypass bus bottlenecks
  Today's standard backplane bus systems offer low-cost, off-the-shelf hardware and design flexibility but have severe bandwidth limitations. To increase data rates and retain the advantages of the bus system, designers are bypassing the bus and directly transferring data between subsystems.
  --Warren Webb, Technical Editor

Design Features

• Chip place-and-route tools lay it on the line
  The final step in ASIC implementation is defining your chip's physical layout. With interconnect-dominated deep-submicron designs, the tools and techniques you use determine whether your design is successful.
  --Jim Lipman, Technical Editor

• Product Preview:  The Embedded Systems Conference
  Plenty of new products will be on display at the upcoming Embedded Systems Conference, which runs from March 31 to April 2 in Chicago.

• Use logic-analyzer setup/hold triggering to ensure timing margins
  With a logic analyzer that offers setup/hold triggering, you can easily measure system timing margins. Straightforward examples explain how to do it.
  --Colin L Shepard, Tektronix Inc

• Electromigration wreaks havoc on IC design
  Current IC-design practices make perfect conditions for electromigration, which causes broken connections. A thorough understanding of the problem and its prevention help prolong an IC's life.
  --Jim Lloyd and David Overhauser, Simplex Solutions Inc

• The right motor can position your application for success
  To design a product that uses motors for position control, you should understand the strengths and weaknesses of several motor types. Then you can choose the best motor or motors and begin selecting or designing a suitable controller.
  --Chuck Lewin, Performance Motion Devices Inc

Leading Edge

• New DSP architecture highlights atomic read-modify-write and real-time emulation
• Floating power manager frees you from ground's constraints
• 1-Gbit Ethernet switch chips incorporate layers 2 and 3
• Low-density flash memory targets EEPROM
• New EDA toolkit boosts CDMA design
• Ultrathin touchpad has pen input, mouse functionality
• Budding FPGAs beat last year's crop
• Debugging tools combine logic analysis, emulation

• Logic-synthesis tool goes triple speed
• Speedy programmable-logic tools
• Three functions in one IC meet many mundane interface needs
• Novel RF packaging cuts cost, boosts performance
• Optical transceivers support increased port density
• Dual-axis, 2g accelero-meter helps you deal with jerks and more
• Desktop drive hurdles 11.5-Gbyte capacity mark
• Calendar

Design Ideas

• PLL implements FPGA-based SDRAM controller
• Comparator uses signal-dependent hysteresis
• Simple LCD interface takes two wires
• Inexpensive logic controls stepper motor

• Low-voltage reset operates below 2.7V
• Alternating LED blinker uses four parts
• Spice generates PSK and FSK signals
• Frequency multiplier improves line readings
• Circular slide rule provides quick results

Products

• New Product Database (registered users only) 

Departments

• ednmag.comment
• Signals & Noise
• Editorial Staff
• Business Staff