April 9, 1998

Supervisory circuit monitors modem connection

J Basílio Simões and Jorge Landeck, Instrumentation Center of the University of Coimbra, Coimbra, Portugal

In telemetry or security applications in which a modem connection automatically establishes itself between two systems, a failure in one of the systems can interrupt the data exchange while the connection remains established until someone physically breaks the line or restarts the failed system. This situation can also happen if your PC crashes during a long-lasting Internet download. To prevent this problem, the circuit in Figure 1 continuously supervises the RS-232C data lines (TxD and RxD) and automatically hangs up the connection when the circuit detects a long period without transmitted or received data.

The TxD and RxD inputs to the circuit (pins 2 and 3 on the D-type RS-232C connector) first drive line receiver IC₁, whose outputs then drive the two inputs of IC₂'s dual retriggerable monostable multivibrator (one shot). When the system establishes a new connection, the first exchange of data triggers IC₂, and positive pulses of duration T_X=0.45×R_X×C_X appear at the 1Q and 2Q outputs. Each new transition on the data lines retriggers the associated one shot, which extends the output pulse for a new period, T_X. In this application, R_X=56kilohms, and C_X=4700 µF corresponds to a period of about 2 minutes.

If a problem arises with one of the systems and it stops transmitting data for a period longer than T_X, the corresponding one shot's output pulse goes low, indicating that the system should hang up the connection. To allow for the self-restarting of the system, another one shot, IC₃, shuts down the modem for a period T_Y, determined by the associated timing resistor and capacitor.

The conditioning circuit for the output signal uses an optocoupler, IC₄, to drive the shutdown input of the modem. If your modem has no shutdown input, you can solve the problem by powering the modem through a relay driven by IC₄. (DI #2186)

Circuit optimizes phototransistor bandwidth

David Magliocco, CDPI, Scientrier, France

A simple circuit can improve the dynamic performance of a phototransistor for use in low- to medium-speed applications as fast as 100 kbps, such as optical isolation of an RS-232C serial line (Figure 1). In low-cost applications that require high voltage insulation, low part count, and low power, you can use consumer components, such as Siemens' SFH421 IR LED with an SFH320 IR phototransistor. The rise/fall-time rating of the LED is 500 nsec, which is fast enough, but the phototransistor's rise/fall time is 5 µsec for the fastest version and 8 µsec for the slowest with a 1-kilohm load.

Phototransistors have less favorable dynamic behavior than do photodiodes because, in addition to the collecting and charging processes, phototransistors also experience a delay stemming from the amplification mechanism (Miller effect). For the rise and fall time  of a phototransistor, the following relationship applies:

where f_T is the transition frequency, C_CB is the collector-base capacitance, V is the gain, and b is a constant whose value lies between 4 and 5. For R_LOAD=1 kilohm, 4<b<5, 100<V<1000, C_CB~2.5 pF, and f_T'~100 kHz, the result is 5 µsec<t_r,f<8 µsec.

A plot of rise time vs load resistance provides a more  practical way to evaluate the maximum transmission speed of Figure 1a's circuit without using additional compensation circuitry (Figure 2). For a 2400 bps serial link with less than 10% error on the bit length, the rise-time estimate is 42 µsec, which corresponds to a 7.5-kilohms resistor.

To get a faster response time, you can use an op amp, but without phase compensation the result is poor. In Figure 1b's circuit, the phototransistor's internal capacitance and the amplifier's gain bandwidth limit the overall speed. To cancel the side effect of the phototransistor's C_CB, the amplifier needs a small capacitor in parallel with R. Choosing the right value for the compensation capacitor is a difficult task, because the current-to-voltage converter exhibits a two-pole response. Also, to ensure stability, you need to consider phase compensation and bandwidth together.

Fortunately, there is another way to get the best of the phototransistor bandwidth. You can isolate the phototransistor's internal capacitance with a transistor (Figure 1c). The transistor, with its low output impedance and its large gain bandwidth, holds the signal voltage across the phototransistor to a stable dc value. The versatile BC847 can do the job, and, with Siemens' SFH320, the circuit can reach a transmission speed of 153.6 kbps. You can't increase the speed beyond this point, even with the fastest op amp, because of the photoelectric delay that the charging and collecting processes cause. (DI #2188)

Technique increases low-cost DAC's resolution

Jeremy Dean, Thomson-Thorn Missile Electronics Ltd, Basingstoke, UK

Cost-sensitive µC applications often employ resistor chains to implement crude DACs. You can extend this method by exploiting the way in which many µCs allow individual output pins to be set to either low ("0''), high ("1''), or floating ("F") states. A converter can thus respond to ternary rather than binary codes.

The resistive network in Figure 1a has three inputs. Allowing each input to be either 0, 1, or F results in the transfer characteristic in Figure 1b. Allowing for two duplicate cases results in 25 distinct output levels. Thus, the technique achieves roughly 41/2 bits of resolution while using only three pins of a µC and five resistive elements. The transfer characteristic is symmetrical about midrail and does not extend to the supply rails, making it inherently suitable for use in single-supply applications. Note that the characteristic is nonlinear, which shouldn't matter for many applications.

A practical circuit implementation uses a single-inline array to form the resistive network (Figure 2). The PIC16C84 (Microchip Technology, www.microchip.com) code in Listing 1 uses a look-up table to convert binary inputs to the required ternary outputs. (Click here to download DI-SIG #2189, which includes this listing and the related look-up table)

You can expand or contract this ternary technique within reason. For example, using four µC pins gives 75 distinct output levels, and even just two µC pins gives seven levels. By saving pins, the technique is ideally suited for use with the PIC12C50X family, which has very limited I/O in an eight-pin package. (DI #2189)

Undersampling extends utility of digital scopes

Robert J Inkol, Defence Research Establishment, Ottawa, ON, Canada

By undersampling the input signal, you can use a digital oscilloscope to digitize and display or collect signal data of even RF and IF signals. To sample a signal without aliasing, you must use a sampling rate that satisfies the relationship

where f_M is the maximum allowable signal frequency and f_S is the sampling rate. If you want the sampled signal data to directly form a high-quality visual representation of the signal waveform, a considerably higher sampling rate is necessary. A practical implication of this equation for high-frequency signals is that you can acquire sequences of signal data for only short periods before the available memory is filled.

However, many high-frequency signals, such as RF and IF signals in communications systems, are bandpass signals whose bandwidths are very small relative to the center frequencies. Consequently, you can intentionally undersample these signals so that their spectral components alias to lower frequencies. To ensure that the spectral components of the signal do not fold over on themselves or become   reversed, you must choose the sampling rate, f_S, such that simultaneous solutions exist for

and

where m=f_L/f_S (an integer) and f_L and f_U are the respective upper and lower bounds for the bandwidth that the signal of interest occupies. The undersampled signal differs from the original signal by a downward shift in frequency of mf_S. In carrying out this concept, you need to disable analog lowpass filters at the oscilloscope input or ensure that the filters have a cutoff frequency high enough to preserve the signal information.

You can apply this concept to practical applications, such as the digitization, storage, and analysis of the RF-signal output from a VHF radio that employs frequency-hopping techniques. In this application, the radio was programmed so that the signal would hop to a carrier frequency of 71.9 MHz at frequent intervals. A bandpass filter centered about 70 MHz with a bandwidth of 5.6 MHz attenuated and band-
limited the transmitted signal. A LeCroy (www.lecroy.com) 9354 digital sampling oscilloscope, operating at a sampling rate of 10 MHz, generates records of 100k data samples. The choice of carrier frequency and sampling rate results in the aliasing of the RF signal to 1.9 MHz. Note that the use of a sampling rate of 200 or 250 MHz would not allow the storage of sufficient data for a complete hop.

You can then use Mathworks' (www.mathworks.com) Matlab to implement signal-processing algorithms for amplitude and frequency demodulation of data sequences associated with individual hops. Figure 1 shows the time-domain behavior of the amplitude and instantaneous frequency measured for a representative hop signal. You can discern the FSK modulation in the switching of the instantaneous frequency between two discrete frequencies. (DI #2190)

Basic stamp computer eases prototyping hassles

Med Dyer, Jabra Corp, San Diego, CA

Many of today's complex ICs use a common three-wire serial interface to provide programming access. These ICs typically end up in circuits that include a µC or a CPU, and the controller or CPU then has the burden of programming the serially controlled parts. During early prototyping of a project, however, the µC or CPU may be unavailable for use: The hardware may be absent, or the complex programming necessary to fully use the CPU may not be in place.

For projects such as these--for which serial programmability is necessary but no resident host exists--you can use a simple and cost-effective prototyping tool: the Basic Stamp II (BSII). A battery-powered BSII is a unique tool for any engineer who regularly works on development projects and with many applications in the lab. With just a few pushbuttons and some minimal interface to the project at hand, powerful portable control is possible--with a minimal learning curve and modest expenditure.

The BSII from Parallax Inc (Melville, NY) is a complete Basic-programmable computer, all contained on a 24-pin DIP module. When plugged into its optional carrier, the BSII offers a serial port for connection to a PC, a battery clip for 9V battery power, a reset button, and plenty of room for the minimal additional circuitry needed for most prototyping applications. The  BSII includes a simple PC-based Basic compiler for developing BSII code, which you download to the BSII's EEPROM for execution. Although a quick read of the BSII manual brings to mind a host of useful applications for the typical R&D engineer, one application is particularly handy: using the BSII to program three-wire serial devices.

One example of a three-wire serial device is the LM1973 three-channel audio attenuator from National Semiconductor (Santa Clara, CA). This part can serve as a three-channel audio pot, and a three-wire serial interface performs channel selection and gain control. The format is simple: The system must first pull the Load line on the LM1973 low and then pulse 16 clocks on the Clock line with a corresponding 16 bits of input data on the Data-in line. The 16 bits of data comprise 8 address bits, which select one of the three channels and 8 attenuation bits, which select the attenuation setting for the selected channel. This data format is most significant bit first with the address bits first and the attenuation bits immediately after. This straightforward format could be difficult to implement in a prototype without a controller, but the BSII makes a "kluge" programmer devilishly simple.

This example uses only one channel of the LM1973, although using all three channels is just as simple. Two normally open pushbuttons--one for up and one for down--provide an active high when depressed (Figure 1). You also need to connect the following three BSII outputs to the digital potentiometer: I/O 8 to Data (Pin 11 for LM1973), I/O 9 to Clock (Pin 9 of LM1973), and I/O 10 to Load (Pin 10 of LM1973)

The meat of the code required for this application comprises two BSII instructions: Button and Shiftout. Button checks the status of a BSII input line and allows for branching according to that status. This example monitors the up and down buttons until one is pressed and then reprograms the LM1973 accordingly. The Shiftout instruction shifts out a data word synchronously along with a clock output. You select the appropriate output pins and specify a most-significant-bit-first protocol, as the LM1973 demands.

This minimal code provides up/down programming on a single channel but is easily expandable to provide other functions, including data readback from the serial device, multiple channels, or custom programming sequences. You can easily edit the code on the PC, debug the code with the BSII connected to the PC, and then download the code and carry it away on the BSII.

Listing 1 is available for downloading.  Click here to download DI-SIG #2178. (DI #2178)

10-kHz VFC uses charge-pump variation

Stephen Woodward, University of North Carolina, Chapel Hill, NC

A diode-capacitor charge pump is the starting point for many voltage-to-frequency-converter (VFC) designs. The circuit in Figure 1 uses a variation on that classic theme to achieve linearity less than 0.05%, micropower operation of approximately 10-µA total draw from a 5 to 36V rail, and bipolar-input capability. The basis for these features is the switchable-polarity, self-compensating charge pump comprising D₁ to D₄, C₁ to C₄, and CMOS switches S₂ and S₃. Although simple in concept, VFCs using diode-capacitor pumps suffer from the need to cope with the nonideal characteristics of diodes used as analog switches.

Temperature-dependent forward-voltage drop, junction and stray capacitance, and reverse leakage current all conspire to limit converter accuracy. The stray capacitance and leakage current are especially troublesome in low-power applications, in which the need to minimize pump-current consumption limits the size of the pump capacitors. Because the total amount of charge pumped in each converter cycle is minimal, the error sources are proportionally more significant and thus harder to control and compensate. The unique pump circuit in this converter comprises two distinct halves: D₁, D₂, C₁, and C₂ generate a frequency-proportional current that closes the VFC's feedback loop, and D₃, D₄, C₃, and C₄ generate an error-correcting compensation current. 

If you assume that C₂=C₂=C₃=C₄ and equality of diode forward drops (V_D) and stray capacitance (C_S), then the net feedback current from the pump is

You not only obtain compensation for the bothersome V_Ds, but also eliminate the effects of stray capacitance in the bargain. Operation of the converter depends on integrator IC₁'s control of multivibrator IC₃. The combination is such that f_OUT=0 when IC₁'s output is 1.2V. If, for example, V_IN>0V, IC₁ ramps negative. As IC₁ ramps through approximately 0.8V, Q₁ begins to conduct, thereby turning on both Q₂ and Q₃. Q₂ drives S₁ to the "plus" polarity state, providing a status signal to the connected system (typically, a gated up/down counter). The status signal indicates the presence of a positive V_IN. S₁ sets up S₂ and S₃ to provide a negative feedback current to C₅. Subsequently, Q₃'s collector current causes IC₃'s f_OUT to increase until 1E­7×f_OUT=V_IN/R₁=4 kHz/V for the values shown, and the integrator is thus balanced.

V_IN<0V causes IC₁ to ramp positive, turning off the Q₁-Q₂-Q₃ transistor trio. This action causes S₁ to generate a "minus" status and set up S₂ and S₃ to generate a positive feedback current. The loop adjusts f_OUT until 1E­7=­V_IN/R₁, as in the case of V_IN>0V. The converter's overall temperature coefficient depends on matching all pump capacitances, including the pc-board contribution to C_S parasitics. A ±5% capacitance tolerance is good enough to reduce the charge-pump temperature coefficient to approximately 50 ppm/°C. The converter linearity is ±0.03%, and the current draw is an unexcelled 6.5 to 10 µA as f_OUT goes from 0 to 10 kHz. IC₁'s approximately 300-µV input-offset spec determines the converter's zero offset. IC₂'s regulation of the 4.55V reference affords good power-supply rejection, yielding undiminished accuracy for supply voltages from 5 to 36V. (DI #2183)

Single IC biases LCD and GaAsFET amplifier

John Wettroth, Maxim Integrated Products, Apex, NC

Operating from a lithium-ion cell or a four-cell NiCd battery, the circuit in Figure 1 provides ­6V bias for LCDs and a separate, quiet negative bias for a GaAsFET power amplifier. This bias combination exists in cell phones, two-way pagers, wireless modems, and many other wireless devices. Not long ago, when most GaAsFET amplifiers required a positive voltage of 6V or more, you could easily obtain the LCD bias by simply inverting the power-amplifier voltage. With the advent of lower voltage power amplifiers and single Li-ion supplies, a negative doubler became necessary for the LCD bias. The various bias-generation techniques in use are generally bulky and require multiple ICs. One alternative is to select an LCD with lower negative bias voltage, but that approach compromises the LCD's temperature performance, contrast, and cost in favor of a simpler bias supply.

For most systems, the approach is to use two ICs: a negative doubling inverter, such as the MAX865, which provides a negative LCD bias of approximately ­6V, and a linear regulator to provide the ­3V GaAsFET bias. However, even two ICs can pose a problem in tiny systems. Moreover, a simple linear regulator may generate too much noise, and noise in the GaAsFET bias can appear in the transmitted RF signal. IC₁, which includes a charge-pump inverter and a low-noise linear regulator in an SO-8 package, generates a quiet GaAsFET bias by design. It operates from supplies as low as 2.5V and produces a negative bias voltage with only 1 mV p-p ripple. You can change the bias level by adjusting R₁ and R₂, according to instructions in the data sheet.

Circuitry in the dashed line provides the ­6V LCD bias. A square-wave signal from the charge pump (Pin 1) adds to the unregulated negative voltage at Pin 3 to form a negative, doubled version of the input voltage. The voltage loss (two diode drops) is minimal because of the LCD's low bias current and the use of low-drop Schottky diodes. The diodes drop approximately 0.2V; a Li-ion cell can thus produce an LCD bias greater than ­6V. (DI #2179)

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