April 23, 1998

EDN's 1998 DSP 16-BIT Architecture Directory

Analog Devices ADSP-2100 

The ADSP-2100 family's CPU handles general processing needs and executes all instructions in a single cycle. All of Analog Devices' 16-bit DSPs are code-compatible and feature an algebraic programming syntax. The processor can execute multiple operations per cycle. The multiply-accumulate (MAC) unit, ALU, and barrel shifter are separate but cannot execute in parallel. Secondary registers shadow each execution unit's registers, allowing fast context switching for interrupt processing.

If you need extended precision, you can address the MAC unit's 40-bit accumulator (includes 8 guard bits) as two 16-bit and one 8-bit register and individually copy the contents to another register. The barrel shifter moves 16-bit inputs left or right into a 32-bit register. The shifter also includes hardware support to perform logical and arithmetic shifts in addition to exponent detection and normalization for block floating point and increasing the precision of a 16-bit DSP. Algorithms such as FFTs in which bits grow from stage to stage use block floating point. A programmer may use the shifter to convert between fixed- and floating-point numbers.

ADSP-2100 family members have X and Y data-address generators (DAGs) and separate program and data buses. Two DAGs provide addresses for simultaneous dual-operand fetches (from data and program memory). Each DAG maintains and updates four address pointers. You may associate a length value with each pointer to implement automatic modulo addressing for circular buffers. While executing from the on-chip memory, the buses feed the X- and Y-data values for each MAC cycle. Thus, you can use program memory as data memory to hold constants for single-cycle MAC processing. The program bus is free for MAC use when the CPU executes from on-chip program memory. The dual-ported program memory allows two memory accesses in one cycle. For access to external memory, the ADSP-2100 has a programmable wait-state generator for zero to seven wait states.

Analog Devices' designers opted for a 16-bit-wide data word and a 24-bit-wide instruction word. The wider instruction word lets the device use more complex instructions and offers more flexibility than does a 16-bit operation code. For external-memory design, the different memory widths mean that if you let three 8-bit-wide memory chips share program and data, you sacrifice every third byte of the data-memory area. Analog Devices integrates as much as 64 kbytes of SRAM around its DSP core to help increase data-transfer efficiency. Many ADSP-2100s also integrate DMA ports that connect to external hosts or external memory. These bidirectional, byte-wide ports can directly access as much as 4 Mbytes of external memory for off-chip storage of program overlays or data tables.

Addressing modes

The ADSP-2100 includes immediate, register-direct, memory-direct, and register-indirect addressing modes. The program sequencer features internal loop counters and loop stacks, enabling looped code to execute with zero overhead. Each address generator supports as many as four circular buffers, each with three registers. The registers define the end, length, and access address. One address generator provides bit-reversed addressing for data only.

Special instructions

The ADSP-2100 can conditionally execute most instructions. A do-until command establishes a sequence of instructions that can be arbitrary in length and nested four deep for repeat operations. In addition to the standard arithmetic and logic instructions, the ALU supports division primitives. Because the ADSP-2100 is a nonpipelined machine, it incurs no penalties for jumps and calls.

Support

Analog Devices supplies an ANSI C compiler, an assembler, a linker, and an interactive simulator. Evaluation boards are available for most ADSP processors. In-circuit emulators are available for hardware target debugging.

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