April 23, 1998

EDN's 1998 DSP 16-BIT Architecture Directory

Hitachi SH-DSP

Although some µP vendors add multiply-accumulate (MAC) units to their devices to allow them to perform basic digital- signal processing, Hitachi grafts a complete DSP to the SH µP. The SH's DSP unit shares the five-stage pipeline with the integer unit; the DSP is not a coprocessor. The CPU contains a fetch and decode unit, which manages the single instruction stream for both the integer and DSP units, routing instructions to the appropriate unit.

The integer unit of the SH-DSP comprises an enhanced SH-2 core that supports the DSP unit (see "EDN's 24th Annual µP/µC Directory," Sept 25, 1997, pg 123). One enhancement is 32-bit DSP instructions; the RISC portion of the SH-DSP still operates on only 16-bit instructions. The SH-2 core uses a Von Neumann architecture, and the DSP unit uses a modified Harvard architecture with a single address space and separate bus for instructions and data. Another significant enhancement of the SH-2 core is the replacement of its 8-kbyte cache with separately addressable X and Y memories. The main integer ALU calculates X addresses, and a separate, 16-bit pointer-arithmetic unit calculates Y-memory addresses.

The SH-DSP has four internal buses. The 32-bit internal bus transfers both instructions and data and can access any region of the processor's 4-Gbyte address space. Separate X and Y buses comprise 15-bit addresses and 16-bit data. The address width is only 15 bits because the X and Y buses can access only aligned word-length data, and the least significant bit is always zero. The SH-DSP also contains an 8-bit peripheral data bus to access memory-mapped registers. A 32-bit external interface provides a direct connection to extended-data-out DRAM, pipeline-burst SRAM, or burst ROM.

The integer and DSP units can't execute instructions in parallel because they share the chip's internal address and data buses. However, the bus structure allows the DSP to access two data operands and fetch an instruction during one cycle. During that cycle, the SH-DSP can execute one ALU operation and a 16×16-bit multiply.

The DSP unit has a register file separate from the integer unit's registers. The DSP unit's registers comprise six 32-bit registers and two 32-bit accumulators with 8 guard bits. These registers are visible only to the DSP unit and to DSP-extended load/store instructions. The DSP unit contains fetch buffers for storing three or fewer instructions of a tight program loop. In the first iteration of the loop, the processor normally fetches and executes instructions, but it also stores the instructions in the buffer. Subsequent iterations fetch from the buffer, reducing power consumption.

Addressing modes

The SH supports immediate, PC-relative, indirect-PC, indirect indexed with automatic pointer updating, direct, and indirect-register addressing. It also provides modulo addressing for the SH-DSP's single circular buffer. Zero-overhead-loop control supports one loop; that is, no nesting. The SH provides no bit-reversed-addressing support.

Special instructions

Instructions perform both arithmetic and logical barrel shifting of data in DSP registers. An instruction performs priority encoding to locate the most significant bit of the source operand; you can combine the result of this operation with an arithmetic shift to normalize a value. The SH also offers conditional instruction execution of some ALU and shift operations. The DSP supports saturation on add, subtract, multiply, and arithmetic left shift.

Support

Hitachi (www.hitachi.com) and Green Hills Software (www.ghs.com) offer a C and C++ compiler/assembler/simulator/graphical-user-interface-based development environment. Hitachi also offers an evaluation board, emulators, and an integrated software-design and -development environment. Hitachi and third-party vendors offer algorithms that include acoustic echo cancellation, Global System for Mobile communications, JPEG, and a set of fundamental DSP libraries.

CardTools Systems (www.cardtools.com) offers NitroVP, a codesign and cosimulation tool that you can use to prototype and model embedded CPU applications, such as the SH-DSP. The tool can cycle-accurately model the processor and its on-chip peripherals, system-level peripherals and other hardware devices, the OS, and application software. One of the most useful capabilities of this SH-DSP simulator is its ability to account for hardware behavior and delays, OS overhead, and memory usage.

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