April 23, 1998

EDN's 1998 DSP 16-BIT Architecture Directory

Lucent Technologies DSP16xx

Lucent Technologies sells its DSP16xx-based products to the modem and wireless market. The main execution unit of the DSP16xx is the data-arithmetic unit, which has a 16×16-bit multiplier and a 36-bit ALU/shifter with 4 guard bits and two accumulators. The dual accumulators let you halve the number of memory accesses and thus are useful for tasks such as autocorrelation lags. The multiplier and adder operate in parallel, and the multiplier has registered inputs and outputs.

The multiply-accumulate (MAC) unit has a three-stage pipeline for fetching, multiplying, and accumulating. The simplified MAC allows the DSP16xx to run at high frequencies. The MAC can shift the multiply result before running it through the ALU/shifter and into one of the accumulators. The instruction-stream pipeline has fetch, decode, and execute stages and runs in parallel with the MAC. The shallow pipeline minimizes the impact of branches to two cycles. The DSP16xx has an exposed pipeline, letting a programmer see data at any point. The programmer controls the fetching data into the ALU and controls the multiply and add. This method minimizes the number of registers to hold temporary data and, therefore, minimizes power consumption and die size.

The DSP divides internal memory into X- and Y-memory spaces. The X memory contains both program and coefficients and would typically become a bottleneck for MACs. However, for fast inner-loop processing, the program uses special instructions to load an inner-loop code block into a 15-instruction cache in the DSP16xx. Alternatively, if a DSP had program, X, and Y memories, an algorithm with few instructions would be an inefficient use of memory. The other advantage of the instruction cache is in power savings. The DSP16xx uses fixed-point, 2's complement arithmetic throughout. The bit-manipulation unit has a 36-bit barrel shifter, two 36-bit accumulators, and four general-purpose 16-bit registers.

The DSP16xx family with its classic Harvard architecture uses three internal buses to move instructions, coefficients, and data in parallel for high-throughput processing. The DSP defines two 64k-word address spaces--one for program coefficients and one for data. Both X and Y buses connect to the same dual-port RAM. If references occur simultaneously to both ports of a bank, the chip incurs a one-instruction-cycle penalty and first performs data access. Memory writes always take two cycles. Analysis of algorithms shows that fewer writes than reads to memory occur for target applications. A special address cycle allows both a read and a write to memory, a compound addressing mode of MAC units.

The DSP has X- and Y-memory address generators, each with its own internal adders and registers to hold address values and offsets. The XAAU has a 12-bit adder, a 12-bit static-offset register, and four 16-bit pointer registers. The YAAU has eight static registers and an adder. Programmers can access XAAU and YAAU registers. The X side has half the number of registers as the Y side because signal processing typically requires fewer coefficient pointers. (The DSP stores coefficients on the X side.) Also, the Y side points to memory that requires more pointers.

Addressing modes

The DSP16xx has register- and memory-direct, register-indirect, and immediate addressing modes; it has no bit-reversed addressing.

Special instructions

Instructions for the DSP16xx include single/block-instruction hardware looping, conditional subroutine call, compare, compound addressing, exponent detection, bit-field extraction, and replacement. The DSP16xx has no rotation instructions.

Support

Lucent Technologies supplies a hardware-development system with an in-circuit-emulator pod. Evaluation and demo boards are also available. The company sells software-development tools, including a C compiler, an assembler/linker, a debugger, a simulator, and an application library. Lucent offers a Linkable Functional Simulator, a DSP simulator model that plugs into system-level simulation tools from EDA vendors. This model allows you to develop your application at the system level using building blocks and to determine whether your design has the bandwidth to perform the task. The company also provides a cycle-accurate model of Lucent's DSP.

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