April 23, 1998

EDN's 1998 DSP 16-BIT Architecture Directory

Motorola DSP561xx

Motorola's DSP561xx delivers single-cycle, two-clock, multiply-accumulate (MAC) operation and offers hardware support for sum of products and vector processing. The DSP561xx 16-bit DSP includes a codec for D/A and A/D voice conversions for digital-cellular and voice communications. The core MAC unit has two 40-bit accumulators, including 8 guard bits, with four 16-bit input registers to hold incoming variables and coefficients. The input registers for a MAC instruction must load at the same time as the previous MAC instruction. You can load the MAC input registers in parallel with the MAC operation. When storing results to 16-bit memory, limiter circuitry optionally saturates the 40-bit accumulator values to ±1, the largest number the accumulator can store.

The DSP561xx has on-chip program RAM and dual-ported data RAM; each has its own address and data bus. The dual-ported data RAM allows the address generator to deliver two addresses per pipeline cycle, yielding two data reads or one read and one write. The address generator has 12 16-bit registers, such as address, offset, and modification registers, for sophisticated addressing and holding interim data values. The core can access the address-generator registers via a global data bus that links the address-generator registers to external memory, peripherals, and a functional bit-manipulation unit.

The chip's 16-bit external bus multiplexes between 64-kbyte program and data memories. The CPU can perform a single access to external memory with no instruction-cycle penalty. When you use slower memory, the chip may request wait states externally or programmably controlled. With a 60-MHz external clock and a 30-MHz basic pipeline cycle, a CPU memory fetch must take less than 33 nsec for single-cycle execution. For MAC processing, portions of the X-memory space supply Y-memory values. The DSP561xx has two data-memory address buses that fetch data from the X-memory RAM and from the external memory for Y-memory values.

Addressing modes

The DSP561xx supports register-direct, memory-direct, register-indirect (postincrement/decrement by 1 or offset indexed by offset), and immediate addressing. The address generator also supports modulo and bit-reversed addressing.

Special instructions

The DSP561xx provides hardware looping using do loops and repeat instructions; only the do loops are interruptible. Other instructions are conditionally exit block loop, division iteration, double-precision multiply step instruction, bit manipulation, and compare.

Support

Motorola sells the Application Development System with in-circuit-emulation operation using the DSP's on-chip emulation features. The on-chip emulator port lets external hardware set breakpoints, single-step registers, and read/modify memory or registers. You can configure the chip to run from external RAM for development. Third-party hardware tools are also available. Motorola supplies a Gnu C compiler and debugger, an assembler/linker, and a simulator. Third-party vendors supply data-acquisition and filter-design packages, as well as OS software.

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