April 23, 1998

EDN's 1998 DSP 16-BIT Architecture Directory

Motorola DSP568xx

The DSP568xx combines µC functionality with a programmable DSP. The DSP family's parallel-instruction set controls three concurrent execution units within the 568xx's three-stage pipeline: the data ALU, the address-generation unit (AGU), and the program controller. Three internal address and four internal data buses support data transfers. The general-purpose µC-style instruction set with its flexible addressing modes and bit-manipulation instructions enables you to write control code without worrying about DSP complexities.

The data ALU provides single-cycle multiplies and multiply-accumulate (MAC) instructions with 36-bit accumulation (4 guard bits), as well as a set of logical and arithmetic operations. The ALU contains 0, Y0, and Y1 input registers (X); two accumulators, which can also serve as input registers; a MAC unit; a 16-bit barrel shifter; and automatic saturation logic. You can write ALU results back to either of the accumulators. Additionally, if you don't expect the ALU result to be 36 bits, then the result can go directly back to one of the three input registers without corrupting an accumulator value.

The AGU supports DSP and µC addressing modes. The AGU can provide two data-memory addresses with address updates in one cycle. The AGU contains five 16-bit pointer registers (one functioning as a stack pointer), an offset register, a modifier register for circular-buffer support, and two address ALUs (one supporting modulo arithmetic) to fetch two data items from memory every instruction cycle. The stack pointer has several addressing modes, improving compiler performance and supporting structured programming techniques, such as parameter passing and local variables.

The 568xx supports an interruptible hardware do loop on an any-sized block of instructions. In a set of nested loops, a programmer generally uses hardware looping for the innermost loop. Then, you can perform the outer loops using software looping and the 568xx's data ALU register, AGU register, or a memory location to store the loop counter. To improve the performance of software looping, the 568xx supports a decrement instruction that operates directly on X memory and uses a conditional branch operation. Furthermore, Motorola added an addressing mode that requires no address calculation and allows direct access to the first 64 locations in X memory; this approach makes the access faster than a long immediate access.

Addressing modes

The 568xx supports register-direct, short and long memory-direct, seven memory-indirect, and immediate addressing modes. It also supports short-branch offset and modulo arithmetic for circular buffers.

Special instructions

The 568xx performs hardware-do and -repeat looping on one instruction or a block of instructions. Single and dual parallel-move instructions perform memory accesses in parallel with ALU operation, allowing two data-memory accesses while fetching an instruction. The 586xx can perform bit-manipulation operations on any register or memory location, and it can perform single-cycle multiply and MAC with optional rounding, addition, subtraction, and squaring. Using a conditional transfer instruction with a compare instruction implements searching and sorting algorithms. If the specified condition is true, then the DSP performs a transfer from one register to another (for example, to store the array index of the maximum value in an array).

Support

The 568xx uses Motorola's OnCE port for on-chip emulation through a standard JTAG interface. Motorola offers a C compiler, cross-linker-assembler and -simulator package for PC, Sun, and HP platforms. This package includes a graphical user interface, as well as a DSP-56811ADS hardware-development system. DSP-56L811 evaluation modules for PCs and third-party tools are also available.

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