April 23, 1998

EDN's 1998 DSP 16-BIT Architecture Directory

NEC µPD7701x DSP

NEC's µPD7701x features three internal buses for X- and Y-data and transfer buses, a pipelined MAC unit, a barrel shifter, and eight general-purpose, 40-bit register/accumulators.

The µPD7701x has 16-bit data words and 32-bit instruction words. It has dual external-memory ports--one for 16-bit data and one for 32-bit programs--with two distinct 16k-word address spaces for data. The 32-bit instruction word helps to increase code efficiency by allowing a variety of operation parallelism. Memory read and write accesses can take a single cycle, although instruction pipelining may require an extra cycle for some instructions. A programmable wait-state generator allows you to divide each of the three external memory spaces into four regions and control the wait states of each region. The 7701x also supports an 8-bit-wide host interface and two serial channels. You can configure each of these for interrupt servicing or polling and to transfer 8- or 16-bit data. You can configure each of these serial channels as most- or least-significant-bit-first data format.

The 7701x comprises a data unit, a program unit, and a peripheral set. The data unit contains X- and Y-memory units, each of which has an address generator, a register file, and a MAC-execution unit. The program unit contains the instruction-address unit with loop control, interrupt-control logic, program memory, and instruction-decode/control logic. A transfer bus links the two main units. Each main unit connects to an external data-memory interface: 14-bit addresses and 16-bit data for the data unit.

The MAC unit has three 40-bit parallel subunits: a multiplier, an ALU, and a barrel shifter. The MAC unit provides 8 guard bits, but, because the 7701x supports no automatic saturation, your program must manipulate the results to retain accuracy before storing into memory. Unlike many other DSP implementations, the MAC subunits have no dedicated input and output registers. Instead, the MAC is tightly integrated with a set of eight general-purpose, orthogonal registers. The core uses the X, Y, and transfer buses to load data into the general register set; the general register set provides the data to drive the MAC subunits, which can execute concurrently. In effect, the general register set, which is basically a multiport register file, serves as the interchange that links the data to the execution side of the processor.

Two two-word RAM data-memory banks supply the X- and Y-data components for each MAC cycle. Each bank has its own address generator with a set of four address-pointer registers. Each unit also has an index-register link to the main data bus. Through this bus, code can load and modify the pointer and modification registers. Each unit also has a modulo register for circular buffering. Circular buffers can be of arbitrary size with arbitrary increment amounts. Autoincrement and autodecrement can be by one, by the value stored in special registers, or by an immediate value. A special bit-reverse circuit handles bit-reversed addressing for each bank. You must directly load internal RAM under program control. Additionally, the DSP hardware supports automatic interruptible looping with a four-level loop stack that lets code nest so that it can loop under hardware control. The 7701x devotes 64 words of internal instruction RAM to interrupt vectors. Each interrupt handler comprises four instruction words, so you can code a short interrupt handler within the vector itself. You can independently enable interrupts, and the DSP services them on a fixed-priority basis. The program stack supports both call-return and interrupt nesting, which together can total as many as 15 calls deep. You can nest zero-overhead loops of as many as 255 instructions as many as four instructions deep or deeper if you use software to save and restore the stack. You can also nest single-instruction repeats within any of these loops.

Addressing modes

The 7701x supports memory-direct, register-indirect, and immediate addressing. Hardware supports modulo and bit-reversed addressing for each data memory.  

Special instructions

The 7701x supports conditional operations to minimize jumps, parallel register load/store, 1-bit shift-multiply-add, clip result, register-indirect subroutine call, register-indirect jump, zero-overhead single- and block-instruction hardware loop, repeat, floating-point normalization, and double precision. The 7701x lacks bit-manipulation instructions.  

Support

NEC’s Windows-based software tools come with a hypertext help utility. NEC supplies the WB77016 Workbench assembler/linker/loader package. NEC also supplies the SM77016 simulator, which simulates I/O through timing files that you write in a programming language. This simulator allows you to control I/O details, such as inserting data into or extracting data from a running simulation. A PC-based plug-in development board offers in-circuit emulation using the 7701x’s on-chip emulation features. NEC also offers a C compiler for the mPD7701x and has ported the Spox real-time OS to 7701x DSPs.

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