April 23, 1998

EDN's 1998 DSP 16-BIT Architecture Directory

SGS-Thomson D950

The D950 core's triple-level metal CMOS technology lets you embed the core as a megafunction in a gate array or cell-based device that has a 0.35-µm library containing RAM, ROM, and programmable logic arrays. By adding optional peripherals, such as interrupt or DMA controllers, a bus-switch-control unit, and memory for data and instruction, you can customize an application-specific DSP around the core. The key to the core's performance is its operational parallelism, which allows the core to simultaneously perform multicycle functions along with other processor functions.

The D950's architecture comprises a data-calculation unit (DCU), an address-calculation unit (ACU), and a program-control unit (PCU). SGS-Thomson organized these units around three 16-bit buses--two for data and one for instruction. Each bus is dedicated to a 16-bit address bus. Data memory (as many as 128k words of RAM and ROM) maps to the off-core buses. The D950 also maps several noncritical registers in the off-core memory space; this approach allows SGS to add registers without using bits in the instruction operation code. The instruction bus provides access to as much as 16k words of program RAM and ROM; data and instruction buses share a bus-control interface. The D950 has an optional emulation-and-test unit (ETU).

The DCU computes operands, which can be 16 or 32 bits, signed or unsigned. The chip's DCU includes a 16×16-bit parallel multiplier to implement a single-cycle multiply-accumulate (MAC) and other MAC-based functions. Special instructions, or "assignments," support these functions and allow you to simultaneously perform a MAC operation and add a register value to the product register. A 40-bit ALU implements a range of functions with two 40-bit accumulators. The core has a 40-bit barrel-shifter unit and a bit-manipulation unit that handles master-controller-unit processing through bit operations. Both 16/32-bit fractional (signed/unsigned) and 16/32-bit integer (signed/unsigned) word formats are available.

The ACU, with two separate address generators, generates an address for each of the two identical data memories and updates them at each instruction, allowing instruction execution and two register-to-memory moves in one cycle. The ACU also contains two stack pointers, allowing you to perform fast context switching. A D950 instruction uses the two stack registers to save or restore two registers at once.

The PCU updates the program counter (PC) according to the current instruction or internal and external events. It performs program-address generation, instruction fetch and decoding, and exception processing, and supports three nestable hardware loops without size or location constraints. By default, the PC increments by one. The ETU contains three independent sections that share an external interface: an emulation port, core-scan registers, and a test port for production test. Dedicated I/O pins provide access to these sections and allow the ETU to interface with an outside JTAG controller or to function as primary access to the final chip.

You can configure an 8-bit general-purpose parallel port (P0 to P7) as an input or output. A test condition attaches to each bit to test external events; interface pins related to interrupt, low-power mode, reset, and miscellaneous functions provide chip control.

Addressing modes

The D950 supports direct, indirect-linear, indirect-modulo, indirect-bit-reverse (all with postincrement), indirect-indexed, and immediate addressing.

Special instructions

The D950 supports bit manipulation, double-precision calculations, and support-specific coprocessor instructions for integrated coprocessors.

Support

SGS offers a $398 starter kit based on the ST18952 (D950) that you can plug into an application board or into the Aptix environment (www.aptix.com). SGS-Thomson offers a JTAG PC plug-in board with a graphical, windowed, high-level source debugger for emulation. A C compiler, a simulator, and an assembler/linker that run on PC and Sun systems are available, as are VHDL models from Synopsys (www.synopsys.com) and Mentor (www.mentor.com). The D950 is integrated into SPW from Alta Group (www.cadence.com), which allows cosimulation with different models of D950 (VHDL, instruction-set simulator, or emulator). SGS also supplies a variety of algorithms and a basic signal-processing library.

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