April 23, 1998

EDN's 1998 DSP 16-BIT Architecture Directory

Texas Instruments TMS320C5x

The TMS320C5x, which is source-code-compatible with the C2x, operates as fast as 100 MHz with a 20-nsec instruction cycle. The static CMOS TMS320C5x is both an accumulator- and a register-based processor. It has a fixed-point multiply-accumulate (MAC) circuit with a registered 16×16-bit multiplier loading a 32-bit product register. The product register, in turn, feeds a 32-bit accumulator without guard bits. The C5x also has two parallel functional units feeding off the data bus: an independent ALU with a register file of eight auxiliary registers and a bit-manipulation, or parallel-logic, unit (PLU). Multiply and accumulate take one cycle each. The basic MAC cycle involves putting a value into a temporary register, fetching a second value, multiplying into a holder register, and accumulating the result in the next cycle. However, if the TMS320C5x executes a MAC instruction within a hardware loop, the DSP can achieve single-cycle execution.

For single-instruction cycle context switching, the C5x has a separate one-deep shadow-register stack for the major registers (accumulator, accumulator buffer, product and status registers, three temporary registers, index register, and auxiliary compare register). For control applications that need bit manipulation, the PLU runs in parallel with the MAC and ALU circuits. The PLU operations can set, clear, test, or toggle multiple bits in a control/status register or a data-memory  location without altering the accumulator contents. The C5x also has 0- to 16-bit left- and right-data barrel shifters.

A power-down mode minimizes power by shutting down the CPU or the CPU and the peripherals. Pulling down the Hold pin can also force the chip into power-down mode. An interrupt brings the chip up to normal run conditions.

The C5x integrates a synchronous, double-buffered serial port that operates as fast as 12.5 Mbps with independent transmit and receive sections. The time-division multiplexed (TDM) serial port has all of the same features as the standard serial port, yet TDM features make the serial port better for interprocessor communication. The buffered serial port operates as fast as 40 Mbps without CPU intervention. The 8-bit, parallel host-port interface interfaces a host processor to the C5x.

Addressing modes

The C5x supports paged-memory direct addressing, in which 7 bits in instruction concatenate with a 9-bit data-page pointer for accessing data RAM (128 words each page). It also supports indirect, immediate, dedicated-register, and memory-mapped-register addressing. The processor supports automatic circular-buffer addressing for two buffers. The addressing mechanism supports buffer wraparound if the address-generation unit steps on the end of the buffer but not on overshoot.

Special instructions

The C5x supports single and block repeat, load T (multiply) register, and accumulate previous product; load T register, accumulate previous product, and move data; multiply and accumulate; multiply and accumulate previous product; square and accumulate; square and subtract previous product; call subroutine indirect; block move with repeat instruction and program to data, data-to-data memory; table read/write; and test and manipulate bit in memory.

Support

The C5x has a JTAG port for chip testing and in-circuit-emulatorlike debugging control and monitoring. TI supplies a DSP starter kit, an evaluation module, and an emulator based on the C5x's built-in emulation logic. The EVM is a PC plug-in card includes a TMS32C50 DSP with 10k words of on-chip RAM, 2k words of on-chip ROM, and 64 kbytes of external SRAM. The EVM uses embedded scan-based emulation via the onboard test-bus-controller IC. The debugger software can run and halt the C5x and scan in and out all of the bits of each register. TI supplies a C compiler, a source-level C assembler/debugger, an assembler/linker, a simulator, a profiler, and an application library. Third-party hardware and software tools are also available.

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