April 23, 1998

EDN's 1998 DSP 16-BIT Architecture Directory

Texas Instruments TMS320C54x

The TMS320C54x DSPs are TI's highest performance 16-bit, fixed-point DSPs. The C54x DSPs use a modified Harvard architecture that incorporates three buses for data memory and one for program memory; each bus has its own address bus. Two of the data-memory buses are for reads, and one of the buses is for writes from the accumulator output. The C54x can generate as many as two data-memory addresses per cycle using two auxiliary register-arithmetic units. The four internal buses and dual address generators enable multiple operand operations and reduce memory bottlenecks.

The C54x has two 40-bit accumulators. A 40-bit adder dedicated to multiply-accumulate (MAC) operations has a separate 40-bit ALU that feeds the accumulators. The ALU and two accumulators support eight special parallel instructions that execute in one cycle. The ALU also features a dual 16-bit configuration that enables dual single-cycle operations. The 40-bit adder at the output of the multiplier allows unpipelined MAC operations as well as dual addition and multiplication in parallel. The multiplier performs 17×17-bit multiplies to allow 16-bit signed or unsigned multiplication with  rounding and saturation control in one cycle. Single-cycle normalization and exponential encoding support floating-point arithmetic.

The C54x's instruction set complements the parallelism of the architecture. It supports many two- and three-operand instructions, as well as some 32-bit operands. Eight individually addressable auxiliary registers and a software stack aid a C compiler's efficiency. The C54x supports two circular buffers of arbitrary length and location.

A compare-select-store unit contains an accelerator that reduces the Viterbi "butterfly update" to four cycles for Global System for Mobile communications channel decoding.

You can use slower external memories by using the 54x's software wait-state generator. All C54x devices support on-chip dual-access RAM (DARAM) that you can configure as data or program memory. The C54x can access this DARAM twice per machine cycle. TI based the C54x on a static-CMOS process that supports three power-down modes. A PLL allows you to throttle the clock.

Addressing modes

The C54x supports single data-memory operand addressing that also supports 32-bit operands. It also supports dual data-memory operand addressing, which parallel instructions use. It provides immediate, memory-mapped, circular, and bit-reversed addressing.

Special instructions

The C54x performs dedicated-function instructions, such as FIR filters; single and block repeat; eight parallel instructions (for example, parallel store and multiply accumulate); multiply and accumulate and subtract (10 multiply instructions); and eight dual-operand memory moves.

Support

TI offers a $149 DSP starter kit (DSK), an evaluation module and an emulator that supports JTAG scan-based emulation for nonintrusive product testing. The DSK's board allows users to access the C542's host-port interface, buffered serial port, and standard serial port. The DSK also includes a Windows-based debugger, which GO DSP (now owned by TI) created. The company also supplies a C compiler, a source-level C assembler/ debugger, a linker, a simulator, a profiler, and an application library. Third-party tools and application algorithms are also available.

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