April 23, 1998

EDN's 1998 DSP 16-BIT Architecture Directory

Zilog Z894xx

The accumulator-based Z894xx, originating from the Clarkspur core, provides an upward migration path for the Z893xx. Although the code is not binary-compatible, the Z894xx supports most of the Z893xx's instructions. The Z894xx has a four-stage pipeline that delivers single-cycle multiplies and pipelined multiply-accumulate (MAC) instructions. The hardware multiplier performs a 16×16-bit to 32-bit multiply and transfers the result to the 32-bit ALU (with 8 guard bits for the MAC) or reiterates the multiplication. The address pointers can simultaneously address the two data RAMs for loading data into the multiplier.

Zilog's Z894xx contains a bit-field unit (BFU) with a 32-bit barrel shifter that can manipulate 16- or 32-bit values. The shifter can shift or rotate a 32-bit operand left or right and place the result in the accumulator. In addition, the BFU can extract a source-bit field and mask and merge it with the specified destination contents.

The DSP implements a Harvard architecture, providing independent program- and data-memory spaces that the DSP accesses simultaneously through X and Y buses in parallel operations. The chip contains an internal-data (ID) bus and a multiplier-product (P) bus. The ID bus provides access to RAM, the stack, the program counter, the RAM pointer, and the data-address space. The 32-bit P bus provides access to the ALU, accumulator, multiplier outputs, and BFU. You can treat a 32-bit product register as two 16-bit registers. External interfaces include separate address and data buses for simultaneous access of external program and data memory.

The Z894xx provides three 12-bit register pointers for each RAM bank. The chip can automatically increment or decrement these pointers to implement circular buffers without software overhead. The Z894xx implements the same type of codec that the Z893xx devices include.

Addressing modes

The Z894xx supports register, direct, indirect, indirect-with-bit-reversal (useful for some FFT algorithms), and immediate addressing.

Special instructions

The Z894xx performs conditional execution of certain instructions, as well as conditional branching. Unlike the Z893xx, the Z894xx performs repeat (hardware looping) and bit test and manipulation. Instructions can zero all bits in the flag except one of interest and store that value into the accumulator. You can also merge flags into the accumulator without overwriting previous bits.

Support

Zilog offers an emulator, an assembler, a linker, a C compiler, a simulator/debugger, and an evaluation board. Zilog also offers prototype packs to accommodate packaging options.

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