April 23, 1998

EDN's 1998 DSP 24-BIT Architecture Directory

Butterfly BDSP9124/9320

Butterfly DSP's chip set with BDSP9124 DSP and BDSP9320 memory manager performs DSP functions, such as digital filtering, image recognition, image compression, spectrum analysis, correlation, convolution, and adaptive filtering in the frequency or time domain.

The BDSP9124's quad-port architecture includes two bidirectional data ports, a bidirectional acquisition port, and a bidirectional coefficient port. Its 24-bit-wide, multiport data-flow structure eliminates the need for external data multiplexing. This structure also allows single-port asynchronous or synchronous memories to serve each bus.

This design's bidirectional nature is conducive to the development of recursive, single-processor systems that process algorithms by passing the data through the chip several times. With six onboard butterfly units and two 60-bit accumulators, the BDSP9124 architecture differs from single-multiply, accumulator-based DSPs. When performing the high-level instructions, each BDSP9124 moves more than 10 Gbps through its I/O port.

The BDSP9320's memory-management unit provides more than 150 memory-address sequences and system synchronizations. With 20 address bits, the BDSP-9320 directly addresses 1M word of memory, permitting very large arrays, 2-D arrays, or support for as many as 32 independent channels. The chip uses a circular-buffer technique with pointers for multiple-channel processing.

The BDSP9124/9320 supports cascaded; single-instruction, multiple-data; and parallel-processing structures. Two cascaded chips process a complex input stream twice as fast as one. Five chips cascaded perform a 1 million-point FFT at a sustained 50-MHz complex sample rate. The architecture is memory-latency-insensitive.

Addressing modes

The 9320 generates address sequences that you would use to access data memory only for DSP-type algorithms. Additionally, the chip provides 9320 addressing sequences to allow access of data in sequential order for block-data operations.

Special instructions

The architecture minimizes software programming by embedding 26 macro DSP instructions in the silicon. These macros include real and complex FIRj-filter and radix-2, -4, and -16 operations. The instructions use the parallelism inherent in DSP algorithms. This capability allows a 50-MHz BDSP9124 to perform radix-16 butterfly operations in 320 nsec and a 1k-point, complex, 24-bit FFT in 65 µsec. Three cascaded BDSP9124s perform the same operation in 21 µsec.

Support

Butterfly DSP provides PC-based software simulators and evaluation boards. The RTS9124 cycle-accurately simulates the BDSP9124's execution unit, including instruction set, data flow, block-floating-point arithmetic, and I/O data format; the RTS9124 sells for $1500. Butterfly also offers its RTS9320 simulator for the accompanying BDSP9320. You can use the simulator to generate the required addressing sequences to support the RTS9124; it also sells for $1500. For $4900, you can buy Butterfly's simulation accelerator and target-system-development board. The company also provides C compilers.

| 16-Bit | Back | 32-Bit |