April 23, 1998

EDN's 1998 DSP 24-BIT Architecture Directory

Motorola DSP5600x 

The DSP5600x integrates µC buses and architectural concepts with a DSP multiply-accumulate (MAC) core and X- and Y-memory blocks. The µC buses allow the DSP to interface with multiple masters and relinquish the DSP bus to another µC. The µC architecture implies a flexible register set and program model.

Like most other DSPs, the DSP56000 has a versatile external memory bus, standard bit-manipulation capabilities, and the ability to execute directly from external memory with single-instruction-cycle accesses. The chip has no on-chip program ROM, except for a small boot ROM on some versions. However, the DSP56000 can access external memory each instruction cycle without time penalties.

In the traditional sense, the DSP56000 is an accumulator-based machine because all math and logic operations go through the accumulator. However, the architecture does allow bit manipulation on registers and memory. It has a single-cycle MAC unit, but the unit has two 56-bit accumulators (8 guard bits); two sets of two 24-bit registers feed the unit. Before you use the data, you must load it into the MAC registers; however, the MAC takes only one cycle (two clocks) for a multiply and an accumulate. Other registers include control and addressing registers. The memory-mapped control registers are discrete but are addressed by memory location.

Like many other DSPs, the DSP56000 has two identical address generators that automatically access X and Y memories for MAC cycles. Each address generator has a 56-bit ALU and four sets of three registers: Four pointer registers each have an associated offset and modifier register. The modifier registers can specify the type of address-register arithmetic operations, or they can hold data. The modifier registers support a FIFO buffer and bit-reversed addressing.

The processor combines 16-bit addressing with 24-bit words. It has three internal address- and data-bus pairs that allow an instruction fetch and two data accesses in one cycle, thereby avoiding the need for an on-chip cache. A fourth bus, the global data bus, is a simple 24-bit logic bus that transfers data to and from on-chip peripherals. You can switch any of the internal address and data buses into the external 16-bit address and 24-bit data bus; external devices can access internal memory via a bus request to the DSP. When the 56000 stores 56-bit values to 24-bit memory or registers, you can deploy an optional 1-bit shift operation and saturate the value to ±1. Unlike many other DSPs, the DSP56000's X and Y memories have their own address spaces, which include on-chip RAM and ROM for the bottom addresses. An internal bus-switch unit handles transfers between internal buses and the single external bus. The bit-manipulation unit performs bit operations on memory values and address, control, and data registers.

Addressing modes

The 56000 supports register-direct, memory-direct, register-indirect, immediate, and bit-reversed addressing.

Special instructions

The 56000 performs do/end-do, single- or block-instruction hardware looping, bit manipulation, compare, divide iteration, jump if bit clear/set, conditional jump to subroutine, and move program memory. It performs logic operations only on bits 24 through 47 of the accumulator; these bits represent the most significant part of the data.

Support

Motorola offers several low-cost DSP5600x evaluation boards as well as a 40-MHz application-development system. Third-party hardware tools are also available. The 56000 uses a proprietary debug interface, OnCE, in lieu of the standard JTAG interface. Motorola supplies a Gnu C compiler and debugger, an assembler/linker, and a simulator. Third-party vendors supply data-acquisition and filter-design packages, as well as OS software.

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