April 23, 1998

EDN's 1998 DSP 24-BIT Architecture Directory

Motorola DSP563xx

The 563xx is Motorola's highest performance fixed-point DSP architecture. The core uses a seven-stage pipeline (two fetches, one decode, two address generations, and two executions) to achieve single-cycle instruction execution. Although a branch penalty is three cycles, the 563xx supports conditional ALU instructions, which often avoid the need to change program flow.

When the processor executes a single-cycle multiply-accumulate (MAC) operation, the first execution stage does the multiply, and the second stage does the accumulate. The register-based architecture of the 563xx uses an interlocking mechanism that automatically inserts a no-operation (NOP) instruction into the pipe to avoid stalls. This approach permits execution to "catch up" with data dependencies.

The 563xx is binary-code-compatible with the 56000, but the 563xx also supports addressing modes that include address-register program-counter (PC) relative. This mode is useful for multitasking and position-independent code, which lets a programmer deliver and relocate object modules without relinking to the original code. Motorola expanded addressing on the 563xx to the full 24 bits, up from 16 bits on the 56000 family. Unlike the DSP56000, which has a 16-location stack limit, the DSP563xx implements an overflow mechanism for the on-chip hardware stack to off-chip data memory. Although the mechanism prevents unrecoverable stack overflows, the chip takes a two-clock  penalty when externally dumping stack entries.

The 563xx core integrates a six-channel DMA that operates concurrently with the core's execution units and has separate address and data buses. The DMA transfers data among memories (P, X, and Y) or among memory and peripherals or the external host buses (PCI or ISA).

You can convert the device's flexible program RAM to a mixture of program RAM and a 1024×24-bit, eight-way, fully associative instruction cache that you can lock at the "way" level. The instruction cache is useful for large programs that require partial storage in external memory. The cache uses a least recently used sector-replacement algorithm.

The DSP runs at 3.3V but has 5V-tolerant I/O. The static core operates from dc to 80 MHz and uses a PLL with a built-in prescaler that allows dynamic clock throttling. For additional power savings, the core automatically powers down unused memories, peripherals, and core logic on every instruction.

Addressing modes

The 563xx supports register-direct, address-register-indirect, PC-relative, immediate, and absolute addressing.

Special instructions

The 563xx's barrel shifter supports multibit-shift instructions in both directions and by any number of bits. The shifter also supports instructions for bit-stream parsing and generation. The device can conditionally execute all ALU instructions, including zero, negative, and overflow. If any instruction is false, the processor executes an NOP instruction. The 563xx performs 16-bit arithmetic that is useful for handling various compression algorithms, such as LD-CELP (low-delay code-excited linear prediction). Normally, when using a 24-bit architecture for 16-bit arithmetic, performance degrades, because you have to round the 24-bit numbers in software.

Support

Motorola backs the 563xx family with a host of development tools. You can use an application-development system, the DSP5630ADS, to evaluate the chip and debug target systems. The device comes with an assembler, simulator software, and a C compiler. The 563xx's JTAG-based OnCE port allows you to examine all internal buses in real time and record the last 12 change-of-flow instructions. Domain Technologies (www.domaintec.com) and Sonitech (www.sonitech.com) both offer PC-based emulators that use the DSP-563xx's OnCE port. Momentum Data Systems (www.mds.com) and Spectrum (www.spectrumsignal.com) offer 56301-based boards with a PCI-bus interface.

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