April 23, 1998

EDN's 1998 DSP 32-BIT Architecture Directory

Hyperstone E1-32

The hyperstone E1-32 combines RISC and DSP technology in a unified core. The integrated DSP unit, working in parallel with the ALU, can perform DSP calculations while the ALU performs loop counts, address calculations, or load/store operations. Hyperstone based the E1-32 on a two-stage pipeline and can only issue one instruction per cycle. The DSP instructions require two or more cycles to complete, and the ALU executes its instructions during the latency cycles of DSP instructions. You or the compiler must arrange your code to take advantage of these latency cycles. And, because the E1-32 supports no separate X and Y memory blocks, you have to perform all loads and stores during the latency cycles to achieve good DSP performance. The E1-32 has a load/store architecture built around a register set that includes 64 general-purpose local and 22 global registers. Local registers are organized into a 64-word, circular register stack to hold function/subroutine stack frames. The stack is organized into frames of as many as 16 words; the E1-32 keeps current frames on-chip  and automatically pushes them to off-chip memory as the register stack fills up (and pops them back from memory as the register stack empties). For fast parameter passing, the current stack frame can overlap with the previous one with a variable range. To minimize silicon overhead, the DSP unit shares all the E1-32's functional blocks, including the register set. However, the DSP unit does provide dedicated result registers and 32- and 64-bit hardware accumulators. The DSP unit supports 16- and 32-bit data types.

Zero-overhead looping on E1-32 requires you to execute two multiply-accumulate operations per loop and use the latency cycles to perform the address calculations, data loads, and compare instructions. The E1-32's 100-MHz operation helps in this area.

The 4-Gbyte address space divides into four blocks; you can individually configure each block for bus width and timing. The E1-32 integrates a fast-page-mode DRAM controller in one of the block spaces. You can use the other blocks for glueless connection of SRAM, EPROM, or other memory devices, each with their own timing and bus width. A separate I/O-address space also allows each I/O device to have its own timing.

Special instructions

Instructions can be 16, 32, or 48 bits; this variation helps reduce code size. The variable-length instructions, which the E1-32 automatically prefetches, provide constants and native addresses as large as 32 bits. DSP instructions include multiply, complex and real multiply-accumulate and multiply-subtract, and complex addition and subtraction. Other special instructions include test-leading zeros.

Development tools

Hyperstone offers a development starter kit, a PC-based development board, and the hyICE serial connector for stand-alone operation. The $3500 development board comes with as much as 8 Mbytes of DRAM, as much as 512 kbytes of SRAM, and as much as 128 kbytes of EPROM. You can attach your prototype hardware using the board's I/O expansion connectors. The company provides an ANSI C compiler, a source- and task-level debugger, an assembler, a linker, and a software profiler. Hyperstone offers hyDSP, a collection of subroutines that include FFTs, discrete cosine transforms, multidimensional arithmetic, and a variety of digital filters. The hyRTK multitasking, real-time operating system performs pre-emptive task scheduling. The operating system, including an integrated debugging monitor and a floating-point library, takes less than 32 kbytes. Third-party vendors Eonic Systems (www.eonic.com) and Etnoteam (www.etnoteam.com) also provide RTOS support.

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