April 23, 1998

EDN's 1998 DSP 32-BIT Architecture Directory

Siemens Tricore

Siemens' Tricore architecture represents the industry's trend toward a blurring of the distinction between microcontrollers and DSPs (see "Microprocessor and DSP technologies unite for embedded applications," EDN, March 2, 1998, pg 73). This architecture's functional units and its unified instruction set target microcontroller- and DSP-specific functionality. Tricore is a superscalar core with two primary four-stage pipelines; the first bit of every instruction identifies which pipeline that instruction follows. One pipeline does loops, loads, and address-generation arithmetic; the other pipeline does all the math and branches. The execute unit comprises a multiply-accumulate (MAC) module, an ALU, and a tightly coupled coprocessor interface. A third pipeline performs loop control for zero-overhead looping. Tricore supports a mixture of 16- and 32-bit-wide instructions to help conserve code space; each operation code includes a size bit to improve the efficiency of instruction decoding.

Tricore implements a Harvard architecture with separate address and data buses for program and data memories. Tricore is also a load/store architecture with 16 32-bit general-purpose data registers and 16 32-bit address registers. You can concatenate consecutive even-odd data registers to form eight 64-bit registers for extended precision.

Unlike traditional DSPs, Tricore lacks separate X- and Y- memory spaces, which may require you to perform some loop unrolling to achieve the parallel performance of DSPs. As long as data is available for Tricore's execute unit, it can perform single-cycle MACs. The data side of the core has a 128-bit-wide bus to on-chip DRAM, which you can use to save two data and two address registers in one cycle to the cache.

Addressing modes

Tricore supports the typical addressing modes of a load/store architecture, including absolute, base+offset, preincrement, and postincrement. It also supports circular buffers for DSP filters and bit-reversed indexing for FFTs. You must align the start of the circular buffer to a multiple of the data size, which the instruction using the buffer prescribes. The length of the buffer must also be a multiple of the data size the instruction using the buffer references.

Special instructions

The instruction set supports operations on Booleans, bit strings, characters, signed fractions, addresses, signed and unsigned integers, single-instruction multiple-data, and single-precision floating-point numbers. In addition to a plethora of microcontroller-oriented instructions, such as bit manipulation, Tricore supports the traditional DSP instructions, including multiply and MAC, saturate, scaling, and rounding. Tricore also supports packed arithmetic. Conditional add, subtract, and select instructions let the device avoid using conditional jumps.

Development tools

Tasking (www.tasking.com) and Green Hills (www.ghs.com) offer C- and C++-compiler, debugger, simulator, and RTOS support for Tricore. Accelerated Technology (www.atinucleus.com) also supplies a Tricore RTOS. Nohau (www.nohau.com), Ashling (www.ashling.com), Hitex (www.hitex.de), and Lauterbach (www.lauterbach.com) supply Tricore in-circuit emulators. Tasking's instruction-accurate simulator allows you to analyze the basic functionality of your program. Siemens is also working on a cycle-accurate simulator, which the company expects to be available this year. The new simulator implements a flexible cache model that provides options, such as defining start and end addresses, the number of ways and cache lines, and the line size and banks. This simulator also includes branch-prediction logic and determines interrupt latency.

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