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April 23, 1998EDN's 1998 DSP 32-BIT Architecture DirectoryTexas Instruments TMS320C3x
The C3x family does not support IEEE floating-point formats. The C3x format uses an implied sign bit to increase precision. In most applications, the difference in data format is relevant only if you are passing the data to another processor. The TMS320C3x DSP comprises memory/access, central-core, and I/O subsystems. The memory/access subsystem comprises separate program, data, and DMA buses, which allow parallel program fetches, data reads and writes, and DMA operations. This internal busing scheme enables programs to access the next instruction and two data values simultaneously and to transfer data to or from the I/O subsystem in one cycle. The data-address buses share a data bus that can make two sequential RAM accesses in one cycle because the buses run at twice the speed of the processor core. Two 32-word, lockable, on-chip caches automatically load as the DSP accesses instructions from external memory. The two 4-kbyte RAM blocks hold parameters and constants for sum-of-products MAC processing, and a 32-kbyte ROM can hold code or coefficients for MAC processing (C30 only). The central core has its own set of buses to move data and results. These buses move data among internal registers; an integer/floating-point multiplier; a parallel, 32-bit barrel shifter/ALU; and the memory subsystem. The core stores results in extended-precision or auxiliary registers that hold the values. Two address generators in the subsystem generate the addresses to access the data memories. The core registers, eight 40-bit extended-precision registers, auxiliary registers, and key-control registers reside in a central multiported register file. The C3x uses a software stack to support context switching. The third C3x subsystem, the I/O, comprises a single-channel DMA controller (dual channel in the C32) and a collection of peripherals that interlink with the peripheral-address and data-bus set. The memory-subsystem buses pass through a multiplexer and link to the peripheral bus, which serves the DMA controller and peripherals. On the C30, the peripheral bus links to an external expansion bus with a 13-bit address and 32-bit data bus. Addressing modes The C3x supports register-direct, paged-memory-direct, register-indirect, and immediate addressing. A single circular buffer supports circular addressing and bit-reversed addressing for FFTs. The circular buffer requires block-size and base-pointer registers plus an auxiliary register that the buffer shares with X and Y memories. Special instructions The C3x performs single- or block-instruction hardware looping (supports nestable block repeats but lacks automatic save and restore of status); standard branches, which empty the pipe; delayed branches, which wait three cycles before changing program counter; interlocked access instructions for multiprocessing (load/store integer or floating-point value and signal interlocked); computed gotos (dynamic subroutine calls); and conversion of floating-point to integer and vice versa. The C3x can perform bit test. You can specify instructions to execute in parallel. Support TI supplies a full-speed in-circuit emulator and an evaluation module. The C3x lacks JTAG support but has a proprietary five-pin emulation interface. TI sells a tool set that includes a C compiler, an assembler/linker, a source-level debugger, a code profiler, a simulator, and an application library. Third-party tools include C and Ada compilers, multiple OS products, filter-design packages, advanced graphical-design tools, and hardware tools. |
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