May 7, 1998

Circuit translates A law to m law

Rolando Herrero, Instituto Tecnológico de Buenos Aires, Argentina

Two common methods exist to compand voice for transmission through a PCM channel. In Europe, A law involves converting a 12-bit input signal to an 8-bit encoded output. In the US, m law involves encoding 13 bits to 8 bits. You can use a translator to convert from A law to m law (Figure 1). The converter is asynchronous and requires only an 8-bit A law input to provide an 8-bit m law output.

In A law, the input level divides into eight regions in which a uniform 4-bit conversion takes place. Regardless of the region, the output encodes 16 possible values. Each region corresponds to a segment in Figure 2, and the lower values have a better resolution (this figure shows only segments 0 through 5). To encode the input takes 8 bits; 4 bits indicate the uniform converted value in the segment, and the other 4 bits divide to represent the segment value itself (S0 to S7, coded with 3 bits) and whether the signal is positive or negative (1 bit).

Alternatively, with m law, also included in Figure 2, all but the first segments have a wider dynamic range and thus more spaced quantization levels (for 4 bits) compared with A law. Instead of 12 bits, 13 bits imply a wider dynamic range but a worse resolution for low input levels.

Figure 2 also illustrates the loss of resolution when converting the output A of A law to output A' of m law. Depending on the law, either 8 bits (A law) or 4 bits (m law and higher quantization levels) represent the value, therefore, the transitions occur faster around output A than around output A'. For the A to A' translation, the slope of A law is twice the slope of m law.

Although information loss occurs during the conversion of value A, the same is not true for B. For B, the A law and m law slope are the same, and the quantization level is the same. Thus, the difference between B and B' involves only a translation and a change of segment (B in S4, B' in S3). A simple comparison shows that the A value suffers a translation and a loss of information but remains in the same segment after conversion.

The design of the encoder must take into account the A law signal's segment and offset value, as does the following algorithm for which the A law  input signal is PSD, and the m law output signal is QRE, for which P,Q=polarity (1 bit), S,R=segment (3 bits) and D,E=value (4 bits):

If S=0, then Q=P, R=S, and E=D.
If S=1, then Q=P, R=S, and E=D/2.
If S=2 and D<8, then Q=P, R=S­1, and E=D+8.
If S=2 and D>7, then Q=P, R=S, and E=(D­8)/2.
If S=3 and D<12, then Q=P, R=S­1, and E=D+4.
If S=3 and D>11, then Q=P, R=S, and E=(D­12)/2.
If S=4 and D<14, then Q=P, R=S­1, and E=D+2.
If S=4 and D>13, then Q=P, R=S, and E=(D­14)/2.
If S=5 and D<15, then Q=P, R=S­1, and E=D+1.
If S=5 and D>14, then Q=P, R=S, and E=(D­15)/2.
If S=6, then Q=P, R=S­1, and E=D.
If S=7, then Q=P, R=S­1, and E=D.

According to this algorithm, the conversion requires both addition and subtraction, depending on S and D. You can express each subtraction as an addition to implement both in the same circuit. Thus, you can express the algorithm as follows, where CO=Carry out:

If S=2 and D<8, then Q=P, R=S­1, Z=8, and E=D+Z (CO=0).
If S=2 and D>7, then Q=P, R=S, Z=8, and E=(D­8)/2=
(D­16+Z)/2=(D+Z)/2 (CO=1).
If S=3 and D<12, then Q=P, R=S­1, Z=4, and E=D+Z (CO=0).
If S=3 and D>11, then Q=P, R=S, Z=4, and E=(D­12=
D­16+Z)=(D+Z)/2 (CO=1).
If S=4 and D<14, then Q=P, R=S­1, Z=2, and E=D+Z (CO=0).
If S=4 and D>13, then Q=P, R=S, Z=2, and E=(D­14)/2=
(D­16+Z)/2=(D+Z)/2 (CO=1).
If S=5 and D<15, then Q=P, R=S­1, Z=1, and E=D+Z (CO=0).
If S=5 and D>14, then Q=P, R=S, Z=1, and E=(D­15)/2=
(D­16+Z)/2=(D+Z)/2 (CO=1).

The value of Z depends on S: Z=2^5­S. Once you define Z, the algorithm performs the same D+Z operation for each S. The carry-out (CO) signal determines whether R is equal to S or S­1. Therefore, this implementation simultaneously solves two problems. Furthermore, the same technique applies for S=6 and S=7, when Z=0.

In Figure 1, a 3x8 decoder, IC₁, converts S to Z, which IC₂ adds to D. If the CO is a 1, E is (D+Z)/2; otherwise, R is S­1. To choose between both options, the circuit uses the CO signal to control data selectors IC₄ and IC₅. These devices select between two possible outputs: S or S­1 and D+Z or (D+Z)/2, respectively. A second adder, IC₃, implements S­1 by summing the S inputs with 15. The circuit derives (D+Z)/2 by shifting D+Z into the inputs of data selector IC₅. Additional logic ensures that no conversion occurs when S=0 and that E=D/2 when S=1.

The 8-bit input is P0/S2/S1/S0/D3/D2/D1/D0, and the 8-bit output is P0/R2/R1/R0/E3/E2/E1/E0. The schematic doesn't show P0 because this parameter's value doesn't change. The circuit was tested with a Motorola (www.mot.com) MC145554 m law PCM codec-filter and an 8TR641 (AT&T, www.att.com) E1 multiplexer. (DI #2192)

MCS-51 endows MicroLan-like protocol to UARTs

SK Shenoy, NPOL, Kochi, India

mCs such as the 8051 and 8096 and UARTs such as the 82510 provide hardware support for a multiprocessor asynchronous serial-communication protocol (MicroLan). This feature is useful in applications in which a number of processors interconnected in a multipoint configuration jointly perform a task, with a master processor controlling slaves by sending data or commands in a selective manner (Figure 1). The protocol operates as follows:

When the master wishes to transmit a block of data to a slave, it first sends an address byte that identifies the slave. All data and address bytes are nine bits long. An address byte differs from a data byte in that its ninth bit is one (for a data byte it's zero). The communication subsystem normally initializes in a mode where the serial-port interrupt activates only when the ninth bit is one. Thus, no slave receives an interrupt from a data byte. An address byte, however, interrupts all slaves, which then examine the received  byte. Next, the addressed slave switches to a mode in which data bytes also receive interrupts, while other slaves go about their business uninterrupted by the data transfer. The address bytes thus control the data flow into a particular node. Indication of the end of a data block can come from either sending a data-length field at the beginning of the block or from the receipt of another slave or reserved address.

The crucial requirement for realizing The protocol is a means of distinguishing address from data bytes. You can effect this identification in many popular UARTs by using an obscure feature found in most UARTs: the capability to transmit and recognize (with an interrupt on) the break condition. This condition is nothing but a "space," or low, in the transmit line, of a duration equal to or greater than an entire asynchronous character-transmission time, including stop bits (Figure 2). In this scheme, the whole data block (including address) from a master is sandwiched between break characters to form a data "frame" (Figure 3), and the address byte is recognizable as the one that immediately follows a break character.

The Turbo C program in Listing 1 demonstrates the transfer of variable-size messages between two PCs (with 8250-compatible UARTs) using the method described here. Figure 4 shows the 8250 register formats. The procedure works with most other UARTs. Click here to download the the listing DI-SIG #2193. A null-modem cable interconnects the PCs' COM ports. The destination PC accepts only the messages   addressed to it. Note that, although the PCs here interconnect in a point-to-point manner, usually the stations interconnect using balanced RS-422 or tristate drivers in a multipoint configuration, as in Figure 1.

A global variable, Receive_Count, initialized to zero, handles frame reception. Initially, the protocol enables only receive-error interrupts. Each time the routine detects a break, the UART raises a receive-error interrupt, and the ISR (interrupt service routine) then enables the receive-data interrupts. On subsequent receive interrupts, if Receive_Count is zero, the ISR checks if the first address byte matches the station's address. If not, the receiver goes back to the initial waiting state, with the receive-error interrupts enabled and the receive-data interrupts disabled, such that the routine ignores the subsequent data bytes. If an address match occurs, the ISR stores the subsequent incoming data bytes in the receive buffer, with  Receive_Count as index. If Receive_Count is nonzero when the break interrupt occurs, it is an end-of-frame break. Then the routine calls the frame-processing function, Receive_Count resets to zero, and the receiver again reverts to the initial waiting state.

To transmit a break, the protocol sets bit 6 (set break) of the line-control register to one. The UART then takes its transmission line low until bit 6 receives a zero. To make the duration of the break equal to one character-transmission delay, the routine transmits a null (00 hex) character. Bit 6 of the line-control register (transmit machine status) indicates when this delay is over; the break bit then resets. To enable detection of the break, bit 2 of the interrupt enable register (interrupt on receive error condition) sets during UART initialization. Bit 0, set to one, enables receive data interrupts. In the ISR, bits 1 and 2 of the interrupt-identification register indicate the interrupt type.

In this scheme, no CPU overhead is wasted examining each character to detect addresses/packet boundaries. Also, a slave must process only three interrupts per data packet transmitted on the bus, and blocks of data not addressed to the slave do not disturb it. Because the break is not a legitimate data character, it is data transparent; you can use it for binary-data exchange. The packet-boundary detection is immune to data errors. You can make it even more robust by including data-length and check-sum fields in the frame to enable error detection. You can also use parity error detection. Note that the method can support broadcast/multicast message transfer by designating some addresses for these purposes. You can also implement any-node-to-any-node communication by polling the master, as in the SDLC protocol. (DI #2193)

Voltage monitor prevents deep discharge of battery

Roger Kenyon, Maxim Integrated Products, Sunnyvale, CA

The circuit in Figure 1 monitors battery voltages from 2.7 to 5.5V while drawing less than 25 m A. When the voltage reaches a minimum threshold established by R₁ and R₂, (V_TH=2.63V for the values shown), the high-side switch (IC₂) turns off and disconnects the battery from the load.

IC₁ is a voltage monitor with an open-drain latched output. Normally high, the output latches low when the battery voltage drops below V_TH. Once triggered, the output remains low even when the now-unloaded battery voltage rebounds to a level above V_TH. This behavior prevents the oscillation that would otherwise occur as connect/disconnect action causes the battery voltage to fluctuate. To reset the latch, the CLEAR input must go high for a minimum of 1 m sec.

The C₁/C₂/R₃ network applies the latch-clearing pulse when you connect a new battery. Rechargeable-battery applications require other schemes for clearing the IC₁ output, such as an spst momentary pushbutton switch (Figure 2a) or simply a connection via the battery-charger connector (Figure 2b).

To set a different value of V_TH, choose a convenient value for R₁, and then calculate R₂: R₂=R₁xV_TH/(1.204­1). IC₂ limits its switch current at a level that the value of R₄ determines: I_LIMIT=1240/R₄, where R₄ is in ohms and I_LIMIT is in amperes, with a maximum of 1A. For the R₄ value in Figure 1, this limit is 500 m A. (DI #2191)

Add switch-and-LED I/O to DSP's serial port

Stan Sasaki, Twenty-First Designs, Lake Oswego, OR

When you debug an embedded DSP design, it's handy to have a bank of switches and LEDs to simulate inputs or to display intermediate results. You can attach 16 switches and 16 LEDs to the data bus using octal latches and decoded address strobes. However, this connection can be a wiring nightmare--or even impossible if the design does not generate the required control strobes. Most DSP chips have a synchronous serial port that provides high-speed (>10 Mbps) bidirectional communication over five wires. The circuit in Figure 1 provides 16-bit switch and LED I/O using the on-chip serial port of Analog Devices' ADSP21xx family. Some ADSP devices, such as the ADSP2105, have only a single serial port that the target application can use. However, during debug, you can use the pin-compatible ADSP2115, which has two serial ports. You can bring the five signals from the second serial port to a header that attaches to the circuit in Figure 1.

The DSP generates a continuous serial clock (SCLK) in Figure 2. Data shifts, MSB-first, in each direction and is valid on the falling edge of SCLK. For transmission to the LEDs, the DSP asserts the transmit-frame-sync (TFS) line while the 16 bits clock out on DT (data transmit). Cascaded 8-bit serial-to-parallel shift registers, IC₄ and IC₅, capture the data, and the LEDs receive an update on the rising edge of TFS. For switch reception, the DSP generates a receive-frame-sync (RFS) pulse one bit-time before reading the data. RFS latches the switch states into cascaded parallel-to-serial shift registers, IC₂ and IC₃, and the data shifts into the serial port over DR (data receive) on the next 16 SCLK cycles. You can configure the serial port to generate the RFS pulse at a rate divided down from the SCLK frequency.

A single instruction reads the switches or writes to the LEDs. For example, the instruction AR=RXn transfers the last switch value from the receiver of serial port n into the 16-bit accumulator, AR. Note that n can be either 0 or 1, depending on which on-chip serial port you use. Similarly, the instruction TXn=AR transfers the 16-bit value in AR to the transmitter of serial port n, and on to the LEDs. You must configure the serial port to operate with the frame-sync types and signal polarities the circuit expects. In this case, the 16-bit value you must write to the serial port n control register is 6FCF. Because 16 LEDs can draw more than 100 mA, you may need to provide external power if the circuit under test cannot supply the necessary current. Because HC parts operate at 3 and 5V, this circuit works for both 3 and 5V ADSP devices. However, for 3V operation you may need to lower the SCLK speed to meet HC performance. (DI #2196)

DSO-triggering scheme is cheap and efficient

Robert Perrin, Z-World, Davis, CA

Although a logic analyzer is useful in troubleshooting a new design, nothing beats a digital storage oscilloscope (DSO) for the ability to see bus levels and timing. However, the trigger mechanisms on most DSOs are not  sophisticated enough to trigger on a specificm P bus state. For example, you may need the DSO to trigger on a specific address while the m P is attempting to read from it. This operation would correspond to the start of some code segment you're interested in observing. Most DSOs cannot provide such triggering. Figure 1 shows a circuit that generates a trigger on a specific  mP bus condition.

The flash IC serves as a decoder. The entire address space is filled with zeros, except for a single one at the address that corresponds to the mP bus state of interest. The DSO can trigger on the D0 line of the flash chip, and begin recording events at the bus cycle of interest. Shorting blocks, used with JP0 through JP16, configure the address pins corresponding to the trigger condition. The mP bus signals required to detect the trigger condition attach to the open address lines in the flash IC. You can program multiple bus conditions to generate a trigger on the same data line. Other data lines can generate additional trigger conditions.

The design in Figure 1 uses a 70-nsec flash chip. The speed is actually irrelevant, because DSOs can acquire and display pretrigger information. The absolute timing of the trigger is arbitrary. The relative timing of the bus signals is the parameter of interest. The DSO displays pretrigger and posttrigger data properly. As a result, you'll have a solid picture of the bus signals for evaluation. The design in Figure 1 uses a ZIF socket to hold the flash IC; thus, reprogramming is easy. In addition, the test pins in Figure 2 make it easy to grab signal lines from PLCC test clips, while providing a 0.025-in. square post pin to which the logic analyzer can connect. (DI #2197)

Piezo device generates buzz, beep, or chime

Dennis Eichenberg, Parma Heights, OH

Piezoelectric buzzers, such as the Murata (Smyrna, GA) PKB5-3A in Figure 1, make excellent alarms. They're compact, lightweight, efficient, and reliable. However, a piezo alarm is a dc device; it requires additional circuitry to operate from an ac source. The circuits in Figure 1 provide a simple and inexpensive way to obtain the dc drive. The W04G full-wave bridge rectifier produces a full-wave dc waveform from the 120V ac line. The 100ohms resistor protects the circuit from surges when you first apply power. The 1N4733 5.5V zener diode protects the buzzer against high-voltage excursions. The 1-mF capacitor provides filtering for the buzzer.

The circuit in Figure 1a produces a true buzzer sound. The addition of an F336HD flashing LED (part number 276-036 at Radio Shack) in Figure 1b changes the alarm to a beeper, and it also provides a visual alarm. The LED produces a constant pulse of light at approximately 1 Hz without the addition of a time-constant capacitor. The LED starts immediately when you apply power, and it's insensitive to temperature variations. The addition of a 35-mF capacitor in parallel with the buzzer (Figure 1c) changes the audible alarm to a pleasing chime. The value of the capacitor is not critical; you can obtain various sound effects by varying it. (DI #2194)

| EDN Access | Feedback | Table of Contents |