May 7, 1998

WHAT'S HOT IN THE DESIGN COMMUNITY

Instrumentation software: no, it's not from Microsoft

Version 5.0 of the visual-programming language, HP VEE, comes from Hewlett-Packard. But the company integrates the package so well with Microsoft applications that you're likely to think the product comes from Microsoft. An HP VEE program can control any application that exposes ActiveX objects. For example, a VEE program can send data to an Excel spreadsheet for further analysis or a Word document for creation of a report. VEE programs can also retrieve data from Access databases and send e-mail via Outlook to warn of the occurrence of specified events. You can also write as much or as little of your VEE programs as you choose in Visual Basic for Applications. Thinking more of corporate intranets than the Internet, HP includes a Web server through which users can monitor VEE programs remotely using the hypertext-transfer protocol (HTTP). Besides supporting all the customary means of interfacing instruments to computers, Version 5.0 also supports the use of IEEE 1394 to control VXIbus instrumentation.

The Windows 95 and NT versions of VEE 5.0 cost $1395. Versions for HP-UX cost $2595 and lack ActiveX support. For nonprofit colleges and universities, a 40-seat license costs $698. You can download a free trial version from www.hp.com/go/hpvee.

--by Dan Strassberg

Hewlett-Packard Co, Palo Alto, CA, 1-800-452-4844, ext 5778, www.hp.com/go/hpvee.

Device gives new perspective to 3-D performance, quality

S3 focuses on single-cycle trilinear filtering and Microsoft-blessed texture compression to differentiate its Savage3D graphics accelerator in the increasingly crowded high-end, desktop-PC 3-D graphics market. Savage3D's deeply pipelined Advanced Graphics Port (AGP) 2X interface supports optional execute mode and tolerates latencies as long as 250 clock cycles. S3-estimated 6-to-1 compression ratios should be welcome news to software developers who might otherwise require the AGP 4X mode for reasonable frame rates in their upcoming texture-intensive games.

S3 claims that its lossy compression approach only minimally impacts graphics quality and promises software-vendor-support announcements at the Computer Game Developer Conference (CGDC), which will take place this month in Long Beach, CA. Performance estimates include a 125 million-pixel/sec fill rate with all graphics features enabled and a 5 million-polygon/sec triangle-setup engine, assuming 50-pixel triangles with 50% of them back-facing.

With a 250-MHz integrated RAMDAC, Savage3D supports resolution as high as 1600×1200 pixels at 85 Hz, but the local memory tops out at 8 Mbytes. This fact both restricts color depth at high resolutions and forces a greater reliance on AGP-based texture-map fetches from system memory. Local-memory options are synchronous DRAM or synchronous graphics RAM as fast as 125 MHz, but double-data-rate support will have to wait for the next generation. The on-chip texture cache size is 8 kbytes. Savage3D also offers an on-chip NTSC/PAL TV-out encoder, soft digital-versatile-disk support, and a 60-MHz video port. Price is $35 (10,000), and Savage3D is now available for sampling; the company targets production for July.

Microsoft, in response to unhappy developer feedback to its lack of commitment to a shipping date, has officially committed to delivering a widespread beta version of DirectX 6 at CGDC and a production release by the end of July. This date is significant because it gives DirectX-based game vendors enough time to finalize their software in time for the all-important holiday season. However, Microsoft will not ship DirectX 6 in Windows 98 but will include it in Windows NT 5.0.
Along with S3's texture compression, Microsoft will incorporate bump-mapped texture technology from TriTech Microelectronics (www.tritechmicro.com) in DirectX 6. Unlike OpenGL, however, neither Direct3D 5.0 nor 6.0 support optional hardware acceleration of geometry and lighting calculations, relying exclusively on software executing on the host CPU.

This decision should be good news to Intel (www.intel.com) with its upcoming Katmai floating-point multimedia-extension instructions, as well as AMD (www.amd.com), Cyrix (www.cyrix.com), and Integrated Device Technology (www.idt.com), which offer their own variations of these instructions.

--by Brian Dipert

S3 Corp, Santa Clara, CA. 1-408-588-8000, fax 1-408-980-5444, www.s3.com.

Microsoft Corp, Redmond, WA. 1-425-882-8080, fax 1-425-936-7329, www.microsoft.com/directx.

Sensor interface measures temperature here and there via SMBus

You often have to know the temperature both at one location, such as an area of a pc board, and at a second remote site, such as an onboard µP. Using the MAX1617 from Maxim Integrated Products, you can do this task with one IC with its integral sensor, plus an inexpensive diode-connected transistor, such as a 2N3904, as the remote sensor. The 16-pin QSOP device operates from 3 to 5.5V and requires 70 µA for operation and 3 µA in standby mode. It reports readings via the System Management Bus (SMBus); you can program in undervoltage and overtemperature alarms for both local and  remote readings via the bus as well. Accuracy for this $4.13 (1000) device is ±1°C for the local reading and ±3°C for the remote reading, including the uncalibrated transistor, over the 60 to 100°C range; local and remote accuracies are ±3 and ±5°C, respectively, over the ­40 to +125°C range.

--by Bill Schweber

Maxim Integrated Products, Sunnyvale, CA. 1-408-737-7600, www.maxim-ic.com.

Hardware, software advance PC-graphics realism

Hot on the heels of the introduction of Nvidia's Riva 128 ZX, the latest proliferation of the vendor's first-generation, 128-bit graphics architecture, comes the second-generation Riva TNT. Similar to  3Dfx Interactive's (www.3dfx.com) Voodoo 2, the Riva TNT's dual parallel 32-bit pipelines can process two pixels and apply two textures to a polygon in one clock cycle. This logic complexity requires more than 7 million transistors and a 12-kbyte cache but results in a peak fill rate of 250 million pixels/sec.

Other notable Riva TNT features include an on-chip, 250-MHz Palette-DAC that can drive a true-color, 24-bit display with resolution as high as 1600×1200 pixels at 85 Hz; a 24-bit Z-buffer; and an 8-bit stencil buffer. The Riva TNT supports high-quality, eight-tap anisotropic filtering (but not as a single-cycle operation) and fully implements the Advanced Graphics Port 2X bus, including sideband addressing and pipelining. Frame-buffer sizes range from 4 to 16 Mbytes, and memory options include standard and double-data-rate synchronous DRAM and synchronous-graphics RAM as fast as 200 MHz.

Nvidia also claims the Riva TNT renders as many as 8 million polygons/sec but doesn't specify the size and complexity of each polygon or what percentage of them the Riva TNT immediately discards because they're back-facing. This bandwidth is also several times higher than the Pentium II processor's realistic ability to generate polygons. A 3D WinBench analysis of the Riva TNT will have to wait until the end of the second quarter, when Nvidia hopes to offer the device for sampling. Nvidia predicts high-volume production by the end of the third quarter at $45 (10,000).

The OpenGL Architecture Review Board has formally ratified and released its Version 1.2 specification, which adds support for the native Windows RGB byte-ordering format, removing the need for pixel swapping and thereby boosting Windows application performance. Additional enhancements, such as separate specular color and texture-coordinate edge clamping, improve visual quality. Optional packed-pixel formats, multiple levels of texture detail, and other vertex features also boost speed. OpenGL 1.2 adds support for 3-D textures and the imaging feature set, a more formal version of OpenGL's extensions.

--by Brian Dipert

Nvidia Corp, Sunnyvale, CA. 1-408-617-4000, fax 1-408-617-4100, www.nvidia.com.

OpenGL ARB, Mountain View, CA. 1-650-960-1980, fax 1-650-961-0595, www.opengl.org.

ADSL driver/receiver pumps up the current with fast-slewing drive

Successful ADSL deployment requires a DSP, a codec, and a physical-line interface, which has some aggressive current-drive and slewing requirements. Texas Instruments designed the THS6002 line driver/receiver for this and other line-interface and communication applications.

Featuring two drivers and two receivers, the IC has a 200-MHz driver bandwidth and 1000V/µsec slew rate at gain of 2. It can drive a 50ohms load with a peak current as high as 400 mA and supports a differential output voltage as high as 40V. On the receiver side, bandwidth and slew rate are the same as for the drivers, and THD is ­70 dB at 1 MHz.

To minimize crosstalk at these high speeds and current levels, each of the four amplifiers on the THS6002 has individual power-supply pins, allowing you to bypass each one separately. Additionally, you can use the drivers and receivers in differential and single-ended modes to further suppress noise levels. The THS6002 is available in a thermally enhanced SOIC using a TI-proprietary design with an exposed thermal slug under the package that is flush with the package bottom, which you solder to the copper foil of the pc board. All of the IC's pins are active; none are devoted exclusively to heat sinking. This configuration allows the $5.67 (1000) device to fit into a 20-pin package.

--by Bill Schweber

Texas Instruments Inc, Dallas, TX. 1-800-477-8924, ext 4500, www.ti.com.

Switch IC lets you sense when the force is with you

Implementing Kelvin force/ sense connections in automated test equipment, power supplies, and calibrated circuits requires high-current, low-resistance switches for the voltage force lines but can tolerate higher resistance signal paths for the sensing or switched guard signals. The MAX4554 through MAX4556 series of ICs from Maxim simplifies meeting these requirements, packaging various switch combinations in one package. The MAX4554 comprises two force switches and two guard switches in a triple-pole/single-throw NO configuration; the MAX4555 has two force and two sense switches in a spst NC configuration; and the MAX4556 has a single force switch and two sense switches in a spdt configuration.

The ICs operate from a 9 to 40V supply or dual ±4.5 to 20ohms supplies. Leakage current for any switch in the off state is 0.25 nA at 258C, and power consumption with ±15V supplies is 1µW. When operating with that pair of nominal supply rails, the on-resistance of a force switch is 6ohms maximum and is matched to within 1ohms of its partner in a device; the corresponding sense-switch figures are 60ohms maximum resistance with pair matching to 8ohms. Prices for these 16-pin ICs begin at $2.42 (1000).

--by Bill Schweber

Maxim Integrated Products, Sunnyvale, CA, 1-408-737-7600, www.maxim-ic.com.

Chip integrates T1/E1/J1 framer, analog line interface

The single-channel T1, E1, and J1 PM4351 framer from PMC-Sierra integrates an analog line-interface unit. The PM4351, or COMET (COMbined E1 and T1), facilitates a single- board design for North American, European, and Japanese telecomm applications, such as wireless transceiver base stations, digital loop carriers, frame relay, and Internet access. The global primary-rate framing and short- and long-haul line-interface parameters are software-selectable. A COMET application design guide is available on PMC-Sierra's Web site.

COMET integrates three HDLC controllers, each with 128-byte transmit and receive buffers to support ITU-T G.964's V5.1 interface for E1. COMET integrates pseudorandom binary-sequence (PRBS) capabilities to perform periodic line maintenance. The device then generates performance reports for monitoring T1 line quality while in service.

COMET uses a 14×14-mm, 80-pin PQFP and meets ­40 to +858C operating-range specifications. The PM4351 uses a 3.3V power supply and costs $15 (10,000).

--by Stephen Kempainen

PMC-Sierra Vancouver, BC, Canada. 1-604-415-6000, www.pmc-sierra.com.

Supply regulator corrals DSP conundrum

As DSP supply currents dropped from 50 mA/MIPS in the early 1980s to their current value of about 1 mA/MIPS, overall currents have risen because the DSP capabilities have increased disproportionately, despite lower supply voltages. To address the needs of systems using the TMS32062x, TMS320C67x, and multiple TMS320C54 DSPs, Texas Instruments has developed the TPS56xx family of synchronous buck-regulator ICs, which can power both the DSP functions as well as other subsystems in the larger product. Proper use of the controller, which can directly drive 2A MOSFETs, lets you achieve typical and maximum efficiencies of 90 and 95%, respectively.

Load transients are a major factor affecting supply design for DSPs--and µPs--so TI designed this family to vary its nominal 500-kHz oscillator frequency for fastest response while maintaining high efficiency. You can also tailor hysteresis levels via an external resistor to match response time and compensation for load transients to your system. The TPS56xx family comprises members having 1.5, 1.8, 2.5, and 3.3V±1% nominal outputs, all operating from an 11.4 to 13V input. All the devices come in 28-lead TSSOP packages with integral exposed thermal pads on their undersides. These pads provide heat sinking and a thermal path to the pc board without the use of thermal grease or additional hardware. Evaluation modules and demonstration boards are also available for this $3.59 (1000) IC.

--by Bill Schweber

Texas Instruments Inc, Dallas, TX. 1-800-477-8924, www.ti.com.

MPEG codec yields lower cost, nonlinear video editing

C-Cube Microsystems introduces the single-chip DVxpress MPEG-2 encoder and decoder with the DVxpress 7112 chip targeting professional-level, nonlinear-editing (NLE) applications; the 7110 targets prosumer (high-end consumer) NLE applications. Digital NLE maintains a single MPEG-2 domain for storage, editing,  and distribution while protecting video quality. The DVxpress enables cost-effective NLE by integrating multiple-stream de-coding capability, real-time special effects, and the first silicon implementation of C-Cube's Frame-Accurate MPEG Editing (FAME).

FAME applies the benefits of MPEG to NLE by delivering precise control over each video frame. Video editors can start/stop, pause/ resume, or seek on a frame-by-frame basis in the MPEG stream, regardless of whether the frame is Intra, Predictive, or Bidirectional (I, B, or B frames in the MPEG notation). Multiple-stream decoding provides independent control over two simultaneous streams for real-time previews and edits. The combination of FAME with multiple-stream decoding and real-time special effects allows for on-the-fly editing of 2-D transition effects, such as fades, wipes, and dissolves, on a frame-accurate basis.

The DVxpress 7110 supports ML@MP (Main Level at Main Profile) for prosumer applications and costs $175 (20,000). The DVxpress 7112 adds ML@4:2:2 (Main Level at 4:2:2 Profile) support and dual-MPEG-stream output. The 7112 costs $300 (5000).

--by Stephen Kempainen

C-Cube Microsystems, Milpitas, CA. 1-408-490-6300, www.c-cube.com.

Arm yourself with desktop codevelopment system

The DeskPOD intellectual-property-modeling system from Simpod can help you codesign and coverify hardware/software systems, such as µPs and application code. DeskPOD comprises a box containing a digital-subsystem board. The board has a zero-insertion-force socket accepting standard PGA packages. You have a choice of three sockets, ranging from 225 to 570 pins, in which you place a chip for software codevelopment. You can program each pin separately using DeskPOD software, eliminating the need to implement different hardware configurations for each chip.

You use DeskPOD for many hardware/software-codevelopment tasks, including hardware modeling, software debugging, and chip in-circuit emulation (ICE). Your target chip can be either an off-the-shelf part or an ASIC. When you run DeskPOD with a simulator, the system offers standard and disengaged operating modes. In standard simulation mode, the modeling system runs synchronously with the simulator at a rate limited by simulator speed. In disengaged mode, DeskPOD runs "free" as fast as 1 MHz until the system needs to interface with the simulator.

Addressing the need for hardware/software codevelopment flexibility, DeskPOD supports 3.3V and 5V devices. A Verilog application-programming interface (API) for Unix is available, and a version for Windows NT should appear midyear. APIs for C code, which you use for embedded firmware or driver development, should also be available in mid-1998, and Simpod is currently considering development of VHDL APIs.

Configuration files for ARM (www.arm.com)µP and DSP Group (www.dspg.com) DSP cores are also available. DeskPOD prices start at $25,000, which includes 8 Mbytes of memory and an Ethernet connection to a host-computer platform or external subsystem. You can load the system with as much as 64 Mbytes of your own memory modules.

--by Jim Lipman

Simpod, Santa Clara, CA. 1-408-330-9300, fax 1-408-330- 9301, www.simpod.com.

Gigabit transceiver targets serial-backplane data switches

IAMCC's quad-channel serial-backplane S2064 transceiver supports 1.3-Gbps-per-channel, full-duplex data transfers. The device interconnects I/O ports to the switch fabric in chassis-based switches for Gigabit Ethernet, Fibre Channel, asynchronous-transfer-mode, synchronous-optical-network, or proprietary point-to-point designs. The CMOS device operates from 3.3V power supply and features a typical power dissipation of 650 mW per channel. A bipolar-process-technology, single-channel device, the S2061, has a typical power dissipation of 1.6W.

The S2064 has four separate full-duplex transceivers that operate individually or locked together for an aggregate data throughput as high as 10 Gbps. The transceiver's operating range is 0.9 to 1.3 GHz. Each of the four 8-bit, TTL-compatible, input and output pairs provides 8B/10B line encoding and decoding to ensure dc-balanced data transmissions. In addition, special error and control characters augment the serial 10-bit data-symbols transmitted on the high-speed, differential-low-voltage positive-ECL (PECL) inputs and outputs.

When you use the S2028 32×32-port crosspoint switch, the transceiver enables serial backplanes with throughput as high as 40 Gbps. The 1.5-Gbps, bipolar S2028 comprises 32 differential PECL inputs that connect to any or all the 32 differential PECL outputs. In addition, a 33rd input serves as a broadcast channel when you connect it to all 32 outputs, or it can supply signals, such as a clock, to individually configured outputs.

The S2064 quad-channel transceiver will be available in August in 208-pin, thermally enhanced BGAs and costs $68 (100). The S2028 crosspoint switch is available now in 224-pin LDCCs and costs $380 (100). The S2061 will be available in June in a 64-pin PQFP and costs $40 (100).

--by Stephen Kempainen

Applied Micro Circuits Corp, San Diego, CA. 1-800-755-2622, fax 1-619-450-9885, www.amcc.com.

Multiprotocol IC trio goes to any port in an interface storm

There's always that design   trade-off: whether to use a smaller, limited-function component or a larger, more flexible one. If you prefer the second choice when you confront a plethora of serial LAN and WAN standards, the LTC1543/LTC1544 interface transceivers and LTC1344A cable terminator can help. This chip set provides software-configurable transceivers for RS-232C (V.28), RS-423 (V.10), RS-422 (V.11), RS-485, RS-449, EIA530, EIA530-A, V.35, V.36, and X.21 protocols, including data signals, clock signals, control signals, and termination. You can select DTE (data-terminal-equipment) or DCE (data-communications-equipment) configurations via three mode-selection pins, eliminating the need for external terminations or switches.

The LTC1543 includes three drivers and receivers for clock and data, plus a charge pump, so the complete chip set can operate from a 5V supply. The companion LTC1544 contains four additional drivers and receivers for control signals, and loop-back test-signal path. Finally, the LTC1344A acts as a programmable cable terminator, invoking the required termination resistors. The trio of ICs, which are available in 24- and 28-lead SSOPs, is certified to comply with European Telecommunications Standards Institute's NET1 and NET2 tests; the set costs $17.65 (10,000).

--by Bill Schweber

Linear Technology Corp, Milpitas, CA. 1-408-432-1900, fax 1-408-434-6441, www.linear-tech.com.

calendar

May 18 to 21

PC Tech Forum, San Jose, CA, details trends in consumer, enterprise, and network computing. Seminars provide insights on 3-D technologies, CPUs, Intel's product strategy, and PC system-design issues. Panels address alternative PC µP strategies; LANs and fast Internet connections for consumers; digital imaging; the server market and technology trends, computing in the future, and more. A four-day package, which includes the conference plus two seminars, costs $2195; registration for only the conference costs $1195. MicroDesign Resources, Sebastopol, CA. 1-707-824-4001.

May 21 to 22

CORBA Fundamentals, Worcester, MA, is a short course that teaches how to write distributed applications on heterogeneous platforms, analyze client/server systems, and develop practical knowledge of today's open standards. Participants should have a basic understanding of object-oriented design and some knowledge of C, C++, Java, or Smalltalk. First-time registration costs $745. Worcester Polytechnic Institute, Office of Continuing Education, Worcester, MA. 1-508-831-5517.

June 1 to 5

ATM Year '98, San Jose, CA, offers tracks covering ATM strategies, the Internet, future technologies, high-performance LANs, products, public services, standards, and voice and telephony. Exhibitors display LAN switches, semiconductors, access devices, application-programming tools, chips, software, broadband-service providers, gigabit-networking products, host interfaces, and more. Four-day program, $1595; five days, $1795. Imark Communications Inc, Framingham, MA. 1-508-628-5484.

Timing-model generators boost static-timing accuracy

Two new EDA tools from Circuit Semantics produce Spice-accurate timing models for input into static-timing analysis tools. DynaBlock and DynaCore build timing models based on transistor-level netlists and include all a design's timing paths. Both timing generators can handle blocks containing more than 500,000 transistors and can produce a 100,000-transistor model in about an hour.

DynaBlock input comprises a configuration file and a circuit netlist. The configuration file defines block-pin definitions, input slopes, output loads, the Spice simulator you will use, and the timing analyzer your model will go to. You also need to specify operating voltage, temperature, and the transistor models the Spice simulator uses. DynaBlock reads a Spice netlist directly, from a schematic-capture tool, or extracted from layout. The netlist can include back-annotated RC information.

After DynaBlock reads the netlist, the tool partitions it into small groups of transistors, called "clusters," with each cluster representing a logic function. Functions range from a simple inverter to a subcircuit containing several hundred transistors. DynaBlock then generates simulation vectors to verify the extracted function. The model generator considers only those vectors that cause an output transition. For clocked functions, DynaBlock also generates vectors to determine setup-and-hold times.

Using an external Spice simulator, DynaBlock then dynamically characterizes the cluster using the gate capacitance of the following cluster as a load and input slopes derived from the preceding cluster. After DynaBlock simulates all the clusters, the tool generates a gate-level model for the entire block to input into your choice of static-timing-analysis tools: PathMill, Motive, DesignTime, or PrimeTime from Synopsys (www.synopsys.com); Pearl from Cadence Design (www.cadence.com); or Velocity from Mentor (www.mentor.com). Using DynaBlock as a preprocessor to static-timing analysis gives you more accurate timing information and lets you input bigger blocks into the timing-analysis tool.

You use DynaCore, a variation of DynaBlock, for timing-characterization and analysis of hard cores. Whereas DynaBlock characterizes a block with one input slope and one output at a time, DynaCore characterizes a core using multiple input slopes and multiple outputs loads obtained from a look-up table. DynaBlock and DynaCore cost $72,500 and $82,500, respectively. Both tools are available for Unix and Windows NT platforms.

--by Jim Lipman

Circuit Semantics, San Jose, CA. 1-408-885-9250, fax 1- 408-885-1067, www.circuitsemantics.com.

Diodes fit medical applications

XRB diodes from Detection Technology target uses in medical, industrial, environmental, and scientific X-ray and beta research. The diodes offer active areas of 2.4×2.4, 5×5, and 10×10 mm and provide charge-collection efficiency, stable operation in harsh radiation environments, and ultralow leakage current and terminal capacitance. For example, one member of the series, the XRB 24s, offers a typical leakage current of 0.08 nA and terminal capacitance of less than 5 pF with 50V bias voltage. Prices range from $15 to $100, depending on quantity ordered and active areas.

--by Fran Granville

Detection Technology, Micropolis, Finland. +358 8 553 6600, fax +358 8 553 6611, www.deetee.com.

| EDN Access | Feedback | Table of Contents |