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May 21, 1998
WHAT'S HOT IN THE DESIGN COMMUNITY
The adoption of the IEEE 802.11 direct-sequence spread-spectrum (DSSS)
standard is spurring new choices in wireless-LAN products that let PC users roam within a
fixed area without data-rate or coverage penalties. One such choice, the Aironet 4500
series from Aironet Wireless Communications,
implements direct-sequence spread-spectrum links for the license-free 2.4-GHz ISM
(industrial, scientific, and medical) band. The products incorporate Type II PC-card LAN
adapters supported by the company's AP4500 wireless access point. This LAN covers as much
as 150,000 sq feet, or nearly 17,000m2, per access point, and adds access
points for covering larger areas.
Based on components of the Prism chip set from Harris Semiconductor (www.semi.harris.com ), this DSSS system reaches data
rates as high as 2 Mbps. Each $595 PC4500 LAN adapter in-cludes scanning functions that
improve load balancing and coverage while consuming just 5 mA in sleep mode and includes
drivers for Windows NT, Windows 95, DOS, and Novell Netware. The access point includes
system-management software and a diversity antenna to maximize SNR and minimize multipath
and dead spots. In addition, the vendor offers site-survey software, which helps you find
the access points in your location to achieve optimal and uniform signal conditions. The
AP4500 access points cost $1795 for Ethernet and $2395 for token-ring interfaces.
by Bill Schweber
Aironet Wireless Communications,
Fairlawn, OH.
1-330-664-7900, fax 1-330-664-7922, www.aironet.com.
IC forms center span of CRT-to-flat-panel-display bridge
Two components from Sage Inc--the
Cheetah 1 and its superset Cheetah 2 LCD-monitor-control ICs--can bridge the gap between
the venerable CRT, driven by analog RGB and sync signals, and flat-panel displays.
Crossing this divide is not just a matter of signal levels, timing, format, or connectors;
it's also a matter of fundamental differences in information content and image-space
characteristics. The Cheetah ICs function as the heart of a pc board that interfaces
between the CRT output and numerous flat-panel formats and sizes, including LCDs and
plasma and field-emission displays. The interface conversion is transparent to your
system, and you need not make any changes in your system ahead of the video output.
The devices, which operate as complex, hard-wired signal processors,
provide spatial processing for resolution conversion and scaling, temporal processing and
timing conversion, and color-depth processing for color transformation. The Cheetah 1
supports images that have resolution as high as the XGA standard and is for
super-twist-nematic and thin-film-display LCD monitors or low-cost flat panels. The
soon-to-be-released Cheetah 2 additionally incorporates image-noise-reduction filters and
an integrated one-screen-display function for user-message overlays. The Cheetah 1 costs
$35 (1000).
An interface board built around a Cheetah IC also includes a
100M-sample/sec A/D converter, clock-recovery circuitry, automatic resolution detection,
physical signal conversion and mapping, and a power supply providing the voltages that
flat-panel displays need. The input to such a board can be from a standard PC CRT with
resolution as high as UXGA, a Macintosh, or a workstation with a high-level or
low-voltage-differential-signal physical link; NTSC, PAL, or SECAM composite video; or
high-definition-TV, digital-video-broadcast, or FireWire digital-video formats. The
estimated price for this board, for which Sage
provides a full reference design and evaluation unit, is less than $100 (OEM).
by Bill Schweber
Sage Inc, Santa
Clara, CA. 1-408-748-0500, fax 1-408-748-8540, www.sageinc.com.
Optical interconnects weave support fabric for
1-Gbps interconnections
Optical interconnections running at 1 Gbps form the underpinning of fast
networks, but it's difficult to achieve these rates with low-cost, easily swapped
connections. Cielo Communications eases the task with
a pair of plug-compatible transceiver modules that comply with the IEEE 802.3z standard
and conform to the GBIC (Gigabit Interface Converter) Revision 4.5 specification. With
these interconnects, your design can achieve required serial electrical-to-optical
conversion and the reverse with hot-swapping and blind-mating capabilities, minimizing
your system downtime. The modules also provide significant EMI/RFI protection--not trivial
at these bandwidths--in this standard form factor. Applications for these Gigabit Ethernet
and Fibre Channel full-duplex interconnects include central-office switching, wide-area
networks, network backbones, and high-capacity storage systems.
Using a short-wavelength, vertical-cavity, surface-emitting laser
(VCSEL) at 850 nm, the GBE-1250SW optical transceiver targets 1000BaseSX optical links. It
supports distances as far as 550m with 50/125-µm multimode fiber or 275m over
62.5/125-µm multimode fiber. Because of the relatively low cost of a VCSEL source, the
transceiver unit costs just $150 (1000). For systems requiring the distance of single-mode
fiber, the GBE1250LW long-wave optical transceiver for 1000BaseLX optical links extends
the 62.5/125-µm distance to 550m and lets you implement 5-km links using a 1300-nm
Fabry-Perot laser and 10/125-µm single-mode fiber. This transceiver costs $400 (1000).
by Bill Schweber
Cielo Communications Inc,
Broomfield, CO. 1-303-460-0700, fax 303-466-0290, www.cieloinc.com.
Videoconferencing processor integrates codecs, control
functions
The VCPex enhanced video-communication processor from 8×8 Inc targets use in videoconferencing systems
and video telephones. The VCPex integrates audio codecs; video codecs; and
video-processor, modem, and control functions on a chip and processes as many as 30
frames/second. An onboard 32-bit RISC processor and 36-bit DSP provide processing power to
support H.320 Integrated Services Digital Network (ISDN), H.324 POTS (plain-old telephone
system), and H.323 (LAN/Internet) ITU standards for video communications. Along with the
VCPex chip, 8×8 provides the software to
implement the ITU standards.
The 40-MIPS RISC µP handles call control, audio and video multiplexing,
and the user interface. The DSP, which 8×8
developed for audio and video processing, performs more than 1.9 billion operations/sec
and handles modem, full-duplex echo- cancellation, and compression tasks. An additional
graphics- and video-mixer engine lets you overlay text and graphics on the video.
A VCPex design kit includes design files for ISDN,
public-switched-telephone-network, and Internet Protocol video phones. You can copy the 8×8 system designs or customize to differentiate
your products. The software tool kit includes an optimizing C compiler; a source-level
debugger; system diagnostics; and support for Windows95, Linux, or Solaris. The VCPex is
currently available in sample quantities. Sample processor chips cost $100; quantity price
is $35 (100,000).
by Stephen Kempainen
8×8 Inc,
Santa Clara, CA. 1-888-843-9898, fax 1-408-980-0432, www.
ViaTV.com.
Application-specific MOSFETs exceed Mobile Pentium
II efficiency mandate
Intel's 1999 Mobile Power Guideline for Pentium II processors calls for
overall power-supply efficiency of at least 88%, but it's a challenge getting your design
to that number working from fundamental MOSFET parameters, such as RDS(on),
gate charge, Miller capacitance, and output capacitance. International
Rectifier eases that challenge with a pair of MOSFETs, the IRF7805 and IRF7807, which
let you achieve efficiencies as high as 92% in 5 and 3.3V dc/dc converters combining the
specifications a Mobile Pentium application needs.
Although their critical on-resistance value is higher than some
competitive devices--11 microhms for the IRF7805 and 25 microhms for the IRF7807--these
MOSFETs yield overall greater efficiency. They accomplish this task by balancing the
sometimes-conflicting and subtle effects of minimizing breakdown voltage, reducing
switching losses resulting from Qgsa, adjusting die size to minimize gate
drive, and keeping Qgd low enough to prevent spurious turn-on and
shoot-through. The pair comes in SO-8 packages and costs $1.25 (100,000); a design kit for
Mobile Pentium II applications is also available.
by Bill Schweber
International Rectifier Corp,
El Segundo, CA. 1-310-252-7105, www. irf.com.
Growing global-routing requirements and sense amplifiers' high power
consumption have so far kept upper end complex PLDs (CPLDs) near the 512-macrocell
complexity level. Philips Semiconductors thinks it
has overcome both of these barriers with the 960-macrocell, 3.3V PZ3960 XPLA2 device. In
defining the architecture, Philips retained
traditional PLD strengths at handling wide decode logic with deterministic timing.
However, the PZ3960's macrocell count may push the device's application base into areas
that FPGAs previously served.
Like the first-generation XPLA CoolPLDs, the PZ3960 blends PAL and PLA
structures in each macrocell. Within a fast module comprising the local Zero-power
Interconnect Array (ZIA) routing multiplexer and four logic blocks, each with 20
macrocells, pin-to-pin combinatorial timings are 7.5 or 9 nsec, depending on whether you
use the available PLA resources. Corresponding register-setup times are 4 or 5.5 nsec with
a 6-nsec clock-to-out latency. If your design needs to use the global ZIA routing matrix,
add 4 nsec to each timing number. Each logic block has 32 dedicated I/O pins and two of
eight total clocks. Philips estimates the
application-dependent PZ3960 gate count at 10,000 to 50,000.
Each logic module's local ZIA has 64 input and 64 output connections to
the global ZIA interconnect, comprising 408 total routing lines. The company relies on its
five-layer-metal, 0.35-µm process to create the chip and on its EDA partners to isolate
you from the device complexity and help you create your designs. Both Philips and Minc (www.minc. com)
offer back-end fitters. The PZ3960 comes in a 492-bump BGA package with 384 I/O signals
and costs $98 (25,000) or $170 (1000). It is available for sampling and should enter
production in the third quarter at roughly the same time that the 320-macrocell PZ3320
becomes available for sampling.
by Brian Dipert
Philips Semiconductors,
Albuquerque, NM. 1-505-822-7629, fax 1-505-822-7804, www.philips.com.
Intel has migrated its Advanced
Boot Block architecture in two directions--one focusing on read performance; the other, on
security (see "Flash
device targets mixed code and data storage," EDN, April 24, 1997, pg
16). The Fast Boot Block product line in 8- and 16-Mbit densities offers a high-speed,
minimal-glue, synchronous-burst interface with roots in the company's 28F016XS. On-chip
configurable burst counters support both standard and interleaved burst order with four-
or eight-access wrap for cache-line fills or a full increment through the memory array.
The interface is generic and usable with a range of embedded processors.
After an initial five-clock random-read latency, subsequent burst-read accesses are
typically single- clock and as fast as 54 MHz. Writes are nonburst. The core operating
voltage is 2.7 to 3.6V, and the 5V-tolerant I/Os can operate as low as 1.65V. The 16-Mbit
device will be available for sampling in June and cost $7.90 (10,000) in SSOPs and $8.90
in µBGAs. Production will begin in the fourth quarter. The 8-Mbit memory costs $4
(10,000) in SSOPs and $5 in µBGAs and will be available for sampling in the fourth
quarter and enter production in the first half of 1999.
Advanced+Boot Block flash memories include two 64-bit
one-time-configurable registers. Intel programs one
location during chip testing with a unique per-device identifier that you can read during
system-board manufacturing. You configure the other register with a data pattern of your
choice via a board tester or PROM programmer. With this approach, Intel intends to
eliminate "cloning" fraud, such as that occurring with some cellular phones.
Intel has also developed yet
another block-locking scheme using RAM instead of flash bits. RAM offers faster and finer
grained locking and unlocking but requires you to store the lock bit matrix elsewhere in
the system because the entire chip powers up locked. Version 2.0 of the Flash Data
Integrator software supports the new blocking scheme. The 16-Mbit Advanced+ Boot Block
memory costs $7.90 (10,000) in TSOPs and $8.90 in µBGAs, will be available for sampling
in June, and will enter production in November. A 32-Mbit version costs $13.30 (10,000) in
TSOPs and $14.30 in µBGAs will be available for sampling in the fourth quarter. Samples
of the 8-Mbit version in TSOPs will be available in mid-1999.
by Brian Dipert
Intel Corp,
Folsom, CA. 1-916-356-8080, fax 1-916-356-2803, www.
intel.com.
You can integrate MicroDisplay's
MD640G1 MicroMonitor reflective display with VGA resolution in consumer-electronics
products, such as watches, pagers, mobile phones, and view finders for digital cameras. It
uses liquid-crystal-on-silicon (LCOS) technology and offers 640×480-pixel resolution. The
gray-scale, 0.5-in.-diagonal display operates in reflective mode, which allows ambient
light to shine through the active-matrix liquid crystal and then reflect from the
silicon-mirror substrate. Because the MicroMonitor is visible in ambient light, it works
well in low-power applications.
The standard CMOS-process silicon substrate allows on-chip integration
of display drivers and VGA- and NTSC-decoding circuitry. The display features a 50-to-1
contrast ratio in direct view using ambient light and a viewing angle as high as 160°.
The display typically operates at less than 15 mW when running 8-bit gray-scale video at a
30-Hz frame rate. The MD640G1 MicroMonitor costs less than $50 (production volume),
depending on the size and function of the display.
An evaluation kit includes a VGA feed-through output that lets you
simultaneously view the video on the miniature display and a full-sized monitor. The kit's
pc board has test points for access to all signals and a removable display to enable
testing the display's mechanical fitting for integration into products or designs. The
evaluation kit costs $999.
by Stephen Kempainen
MicroDisplay Corp,
San Pablo, CA. 1-510-243-9515, fax 1-510-243-9522, www.microdisplay.com.
It's one thing to build a supply or charger and test it, but it's
another thing to fully characterize it with the varying and often fast-slewing loads that
the source will see in an actual application, such as a cell phone or a battery-operated
instrument. A pair of 100W electronic loads, the EL2 and EL3 from Eltest, controlled by a digital serial output port on
your PC, simplifies devising your own test setup. These 2×2×0.4-in. (5×5×1-cm) units
provide 12-bit resolution in load setting, and need just serial-data-input, clock,
data-latch, and chip-select control lines.
You can change the simulated load at high rates with a full-scale step
input settling to ±1% full-scale range in 100 µsec. Maximum dynamic loading rate is 20
kHz with current resolution of ±0.25%. The EL2 has loading current capacity as high as
20A and loading voltage as high as 50V; the EL3's corresponding specifications are 2A and
200V, both as high as a 100W maximum with suitable heat sinking. For higher power
applications, you can operate multiple EL2 or EL3 units in parallel, using the units'
chip-select lines. Each model costs $249.
by Bill Schweber
Eltest Corp,
Mansfield, MA. 1-508-339-8210; fax 1-508-337-4789, www.
eltest.com.
BGA coolers use unique attachment system and dry thermal
interface
Heat-sink assemblies from Chip
Coolers use a patented attachment system to accommodate BGA-based ICs ranging in size
from 15 to 50 mm, as well as 21- and 25-mm Power PC µPs. The attachment system allows you
to attach the heat sink to the IC package with a simple snap-on process. A threaded
clip-and-screw-down as-sembly accepts a mating aluminum heat sink that screws into the
clip. The assembly snaps down and locks into place with a 90 to 180° turn.
The cooling system uses Cool Link: a dry thermal interface silk-screened
directly onto the bottom of the heat sink. It replaces thermal grease; it does not chip,
flake, or crack, and you can't scratch or rub it off. The Cool Link interface expands and
contracts with thermal cycling and does not degrade with time. Cost ranges from less than
$1 to $3.50 (OEM).
by Bill Travis
Chip Coolers Inc,
Warwick, RI. 1-401-739-7600, fax 1-401-732-6119, www.
chipcoolers.com.
A family of heat-sink products from Aavid
Thermal Products provides cooling for Intel's (www.intel.com) Celeron µP, which uses a single-edge
processor package. The heat-sink product family includes passive or active heat sinks,
thermal-interface material, attachment clips, and plastic retention supports. In
configuring your cooling systems, you can purchase either a complete heat sink or any of
the cited individual components.
Passive heat sinks include versions that use straight-fin extrusions for
moderate cooling needs or cross-cut configurations for more demanding cooling
requirements. Active-fan heat sinks use a 40-mm fan; a 50-mm option is available for
maximum cooling. Prices for passive and active units start at $2 and $5.25 (5000),
respectively. Prices for kits, including the sink, Soft Face interface material, an
attachment clip, and plastic supports, start at $5.50 (5000).
by Bill Travis
Aavid Thermal Products Inc,
Laconia, NH. 1-603-224-9988, fax 1-603-223-1738, www.aavid.com.
Vertical gyro uses DSP, MEMS, look-up-table
compensation
The DMU-VGX solid-state vertical gyro from Crossbow
Technology couples MEMS (microelectromechanical-systems) accelerometers with DSP
techniques to provide rate-sensor and six-axis acceleration functions. (For more
information on MEMS, see "MEMS sensors and mechanical gadgets enter the
mainstream," pg 77.) It supplants mechanical gyros, which often have an MTBF as low
as 500 hours. The DMU-VGX has an estimated MTBF higher than 50,000 hours. Software
calculates instantaneous angle data from the rate sensors and uses accelerometers to
correct for drift and provide a gravity reference. The result is functional equivalence to
traditional mechanical gyros.
The device provides stabilized roll and pitch (artificial horizon)
output with a near-instantaneous warm-up rate, as compared with the traditional spin-up of
several minutes. Other six-axis accelerometer/rate-sensor systems provide
direct-acceleration and rotational- rate data but do not provide the stabilized angle
information most gyro applications require. The DMU-VGX includes factory-programmed,
EPROM-based calibration and temperature compensation and a D/A converter that provides
analog outputs. The gyro costs $4000.
by Bill Travis
Crossbow Technologies Inc,
San Jose, CA 1-408-324-4830, fax 1-408-324-4840, www.xbow.com.
June 7 to 11
Supercomm '98, Atlanta, offers more than 250 educational programs,
seminars, workshops, plenary sessions, and keynotes. Seminar topics cover fixed wireless
access; unified messaging for service providers; intranets and the Internet; wireless
interoperability and interconnection; and more. More than 700 manufacturers, suppliers,
and service providers present technologies, products, services, and applications.
International Engineering Consortium, Chicago, IL. 1-312-559-4600.
June 9 to 11
Electro '98, Boston, colocated with Nepcon East, showcases the latest
technologies in the electromechanical, components, interconnection, and packaging
industries. The conference focuses on developments in telecommunications, surface-mount
technology, electromagnetic compatibility, and design for manufacture. The event covers
topics from design through assembly. Nepcon East features more than 400 companies
displaying technological advances in electronic manufacturing. A new demonstration center
offers training opportunities. Reed Exhibition Companies, Norwalk, CT. 1-203-840-4800.
June 15 to 19
Design Automation Conference, San Francisco, presents information on
design products, methodologies, and processes. The conference debuts Silicon Village, a
venue for silicon-device companies to showcase products. A design-methods track addresses
current industry issues, including system design, formal verification, and
hardware/software codesign. A design-tools track focuses on up-to-date CAD-tool R&D.
More than 200 EDA, semiconductor, and hardware vendors exhibit their products. MP
Associates, Boulder, CO. 1-303-530-4333.
Library helps you design cellular-phone chips
You use HP EEsof's W-CDMA
library for designing wideband code-division multiple-access (CDMA) chips for
cellular-phone systems. HP sells the library as part of its Advanced Design System, which
encompasses design tools for analog, RF, and digital technologies. W-CDMA lets you develop
and verify DSP algorithms embedded in wideband-CDMA systems. After you complete
algorithmic development, you use other Ad-vanced Design System tools (priced separately)
to generate HDL code for hardware implementation of the algorithms, test vectors for
testing the hardware, and links to simulators. The W-CDMA library contains a range of
predefined components and testbenches, including functions for encoding/decoding,
interleaving/deinterleaving, framing, multiplexing/demultiplexing, uplink and downlink
generators, interference cancellers, and adaptive antenna design.
Available for use on both Unix and Windows platforms, the W-CDMA library
costs $30,000, but to design with it you need HP
EEsof's DSP Designer tool, which costs $15,000. DSP Designer lets you simulate digital
parameters, such as bit width, for designs you develop with the W-CDMA library.
by Jim Lipman
HP EEsof,
Westlake Village, CA. 1-818-879-6200, fax 1- 408-588-6130, www.hp.com/go/hpeesof. |
