June 4, 1998

WHAT'S HOT IN THE DESIGN COMMUNITY

New 32-bit MIPS core benefits communications

Whereas most MIPS-architecture licensees are busy developing new 64-bit cores, and some are developing cores with 16-bit instruction sets, Integrated Device Technology (IDT) instead does the unusual: It developed a new 32-bit core. The company realizes that a 32-bit core would attract system developers migrating from other 32-bit architectures. The RISCore32300 comprises a five-stage pipeline, similar to that of the RC3000 and RC4000, but IDT has implemented an innovative combination of features. One of the most important features is its ability to perform nonblocking loads, allowing the pipeline to continue execution as the CPU's bus-interface unit processes the load. As a result, the architecture causes no pipeline stall and performance loss if the data item is available before the program attempts to use it. This feature has a significant benefit in communications applications; it allows programmers to hide main-memory latencies during routing or packet processing.

You can also use the nonblocking load for cache prefetch and for performing DMA transfers without performing invalidates and write-backs. IDT implemented this feature as a new hit, called "ignore hit." IDT used this feature to help you get around the MIPS instruction-set architecture's lack of "move-multiple" operations. The 32300 also supports a mechanism to minimize pipeline stalls; in the event of a cache miss, the first word coming in can go directly to the pipeline.

Although the 32300 uses the MIPS II instruction-set architecture, it includes some MIP IV functions. Specifically, it implements those MIPS IV instructions, such as prefetch operations and conditional moves, that are independent of operand size. The 32300 also supports both big- and little-endian data types.

The 32300 executes every instruction, except multiply and divide, in one cycle. To improve the multiply and divide performance, IDT built in a dedicated integer multiply/divide unit. In the MIPS instruction-set architecture, multiply and divide use special destination registers, permitting only one multiply at a time. IDT has enhanced this capability with a three-operand multiply, whereby the operand results go directly to a general register. The unit supports DSP capability and performs atomic multiply-adds (MACs) and multiply-subtract. It also implements count-leading ones and zeros operations. The MAC throughput is one cycle faster than the data latency, so if you use two distinct operands, the operation becomes load-bound.

The 32300's cache architecture is compatible with the 64-bit RC4000 and RC5000. It includes an 8-kbyte instruction cache and a 2-kbyte data cache; both are two-way set-associative and support write-through and -back. For deterministic performance, you can lock the caches on a per-line basis.

The 32300 also delivers a high-speed interrupt response; the CPU gets to the interrupt-service routine in about 230 nsec and has saved-state and a few working registers. Whereas the general MIPS mechanism supports reset, cache/parity error, user translation-look-aside-buffer miss, and general interrupts, IDT lets you define separate interrupts to support software compatibility with your legacy code.

The bus-interface unit provides a direct interface to 8-, 16-, and 32-bit devices. IDT did not base this interface on translation-look-aside-buffer entries but used special registers that your software initializes at reset. The company's reasoning behind this implementation is that attributes such as width and speed are physical, not virtual, attributes; this approach allows the system-initialization software to program these attributes at start-up. One register describes the physical address width; a second register describes tristate characteristics, such as bus-turnaround time. IDT also built in an enhanced JTAG interface that moves in-circuit-emulation capability directly into the execution core. The MIPS standard interface supports this JTAG interface.

The RC32364 is IDT's first standard product based on the 32300 core. Available in a 144-pin TQFP, the 100- and 133-MHz devices sell for $12.50 and $16.50 (10,000), respectively.

--by Markus Levy

Integrated Device Technology, Santa Clara, CA. 1-800-345-7015, www.idt.com.

Transceivers deliver megabytes per second
using milliwatts of power

National Semiconductor's Bus LVDS (low-voltage differential-signaling) family of backplane transceivers addresses the need for speed in Internet and mobile-phone traffic, datacomm and telecomm switching, and base-station equipment. The Bus LVDS family of five interface devices uses the high-speed, low-power, and low-noise advantages of point-to-point LVDS for multipoint bus applications. Bus LVDS enables high-speed data transfers without expensive connectors, backplanes, or cable interconnections because the differential signals tolerate impedance discontinuities. For example, Bus LVDS can drive a 20-card, stripline backplane with low-cost, three-row connectors at 155 Mbps on each parallel bus line, meaning that a 32-bit-wide bus would have 620-Mbyte/second data throughput. Furthermore, this throughput requires only an impedance-matching termination resistor without termination voltage at each end of the bus line to stop reflections. The bus-backplane data rate can be as high as 400 Mbps on each line.

To provide multipoint bus operation, Bus LVDS boosts the bus driver's loop current to 10 mA. The combination of current and termination resistors delivers a 300-mV differential-voltage swing to every card on the bus. Also, the differential driver's balanced output impedance reflects bus noise as common-mode voltage, which the differential receiver ignores. In addition, the driver is in a high-impedance state when powered down, so Bus LVDS tolerates system-card power faults. This high impedance and the nature of the differential receivers also enable fault-free hot insertion of cards into an active data bus.

LVDS affords low power consumption, noise, and EMI because of the current-mode driver, the CMOS process the devices use, and the lack of active bus termination. Also, Bus LVDS has low noise emissions because the current-mode output softens transition edges, low power draw and spikes from V_CC and ground planes, and differential transmission lines that cancel noise. Low power consumption and low noise emissions are important features in equipment such as wireless base stations in remote locations and stackable Ethernet switches in office environments. The driver's constant 10-mA loop current means that the transceiver's power dissipation depends only on receiver switching speed and output drive.

The $8.50 (1000) DS92LV090 nine-channel transceiver includes a feature that reduces propagation-delay skew between channels to ±200 psec across 18-, 27-, and 36-bit-wide buses. The device provides 200-Mbps data throughput on each channel, or 1800 Mbps per device, and comes in 64-pin TQFPs.

The DS92LV1021 serializer and DS92LV1210 deserializer chip ses reduce a 10-bit datapath, plus the clock, into one Bus LVDS link. The serializer drives multiple deserializers on the LVDS link for a data rate as high as 400 Mbps. The 10 TTL inputs and outputs operate as fast as 40 MHz, and the chip set typically uses less than 80 mA from a 3.3V supply. The chip set requires no external encoding, and the serialized bit stream includes the encoded clock for the deserializer to recover. The devices sell for $9.50 (1000).

The $2.50 (1000), single-channel DS92LV010 bus transceiver comes in an eight-pin SOIC and provides 155-Mbps throughput. The 200-Mbps, $3.40 (1000) DS92LV222 bus repeater comes in 14-pin SOICs.

--by Stephen Kempainen

National Semiconductor, Santa Clara, CA. 1-800-272-9959, www.national.com.

DAC's back with hot new EDA tools

EDA's annual big show, the Design Automation Conference, (DAC, www.dac.com), takes place in San Francisco during the week of June 15. Along with more than 200 exhibiting companies, this year's show features the new Silicon Village, populated by silicon vendors with ASIC, programmable-logic, foundry, and intellectual-property (IP) products. Every year, many EDA and ASIC companies use DAC as the time and place to unveil some of the industry's hottest new tools, and this year is no exception. Not surprisingly, many new products address current and upcoming chip- and board-design trends: IP protection, complex-design management, IC-package design, and RTL design. Here are some of the interesting new products you should see if you attend DAC.

Two well-known EDA companies, Summit Design and Escalade, have new products for IP protection, a product area that is new to each company. Both vendors compile secure models of soft cores; you cannot reverse-engineer the compilation, thus protecting the core vendor's IP. Designers can simulate the compiled models as part of their normal design verification.

Summit designed Visual IP (VIP) primarily for core providers. The tool creates and distributes protected IP models and related documentation. VIP includes an IP Model Compiler to create VIP models and an IP Model Manager that reads and simulates the models. The VIP model is a binary file of the HDL model, data-sheet specifications, simulation vectors, and other simulation data. The IP Model Manager, which has an embedded simulator and links to third-party simulators, decodes the VIP model. You use VIP for VHDL and Verilog models and can simulate the protected models on many popular simulators. VIP runs under Windows or Unix with prices starting at $100,000.

IP Guard, Escalade's model-protection tool, works with C, Verilog, and VHDL models. Using proprietary compilation, you can add timing diagnostics, such as checks for setup-and-hold, state-dependent delays, and transition-dependent outputs, into the protected model. Escalade also includes debugging features, including internal-register viewing, instruction tracing, and check pointing, to help verify the models. IP Guard runs on Unix and Windows platforms and has a starting price of $224,000, bundled with 40 hours of consulting time and three copies of DesignBook, Escalade's integrated design-entry, -analysis, and -implementation tool suite.

Addressing the growing complexity of managing system-on-chip designs, two start-ups are launching tools to help engineering teams work together more efficiently. NT-based Simulation Desktop from Simerica is a visual-simulation environment that lets you manage pc-board-based projects and administer component libraries among a work group. Design-team members use the tool to integrate schematics, model sources, and simulators and to generate structural Verilog netlists and test fixtures. The tool offers a SmartSearch feature to let you select models based on your preferences, and you can recognize and configure models based on a knowledge base of model characteristics. Simulation Desktop supports netlist formats from many popular schematic packages. Prices start at $5000.

InfoQuick's WebStir, running on Windows platforms, lets you access component information from many Web sites without launching a Web browser. You use the tool to track parts and associated data in each design for future reuse. With application-programming-interface (API) features, you can also embed WebStir into your EDA tools. The tools' database is the Internet with more than 750,000 parts from more than 125 vendors. You define search parameters and let WebStir retrieve a parts list from the InfoQuick Web site. The current version of WebStir, unfortunately, does not let you include part parametrics, such as operating voltage or bit range, in search parameters; InfoQuick intends to add this feature later. You select parts for which you want further information, and WebStir downloads it for you. WebStir uses a suite of Web crawlers, called Talon, that tracks Web-based component information, indexes and stores the data, searches for new or updated parts, and realigns the information for WebStir. The annual rate for the tool is $12,000 for a server and two floating licenses.

One of the weak links in pc-board design, package design, is getting a boost with new products from Pads Software and Xynetix. Pads' Power-BGA automates the connection of bare die to a pc board. You use the tool for BGAs, chip-scale packages, laminate-based multichip modules, and chip-on-board mounting. PowerBGA features a layout editor with features specific to chip-package design; bare-die definition, including chip size and bond-pad locations; pin, pad, and signal names; netlist integration; automatic wire-bond fan-out; and automated wire-bond diagrams. PowerBGA will be available in the fourth quarter for $15,000 to $35,000.

Interconnect Compiler from Xynetix combines a single-layer any-angle autorouter with automatic net-assignment capabilities to provide automatic routing for single-chip IC packages. The autorouter works with wire-bonded and flip-chip packages. After creating bond-finger locations or die-bump escape patterns in Encore, Xynetix's IC-package-design tool, Interconnect Compiler, automatically routes from the bond fingers or bumps to the package vias or ball pads. The Interconnect Compiler option to Xynetix's $50,000 Encore BGA tool costs $20,000 more.

SOC complexities require an increase of chip-design and -verification tasks at higher levels of design abstraction. More EDA products are becoming available to design at a chip's RTL, letting you eliminate problems and optimize a design before logic synthesis. New tools to look up at DAC include an RTL floorplanner; a design partitioner; an RTL power analyzer; a C-to-HDL code converter for hardware/software codesign; a code-coverage analyzer; and a multilanguage, multilevel simulation environment.

You use Synplicity's HDL Floorplanner for RTL floorplanning on a programmable chip. The tool gives you quick feedback on timing, usage, and routability and passes floorplanning information to your place-and-route tool. The first devices that HDL Floorplanner supports are the Xilinx (www.xilinx.com) XC4000 and Virtex families and Altera's (www.altera.com) 10K series. HDL Floorplanner costs $17,000. Also selling for $17,000, Synplicity's HDL Partitioner partitions large designs across multiple FPGA devices and creates synthesizable netlists for all design partitions.

To supplement its RTL power-analysis tool, Senté now offers Peak Watcher, a tool that lets you identify and analyze peak power consumption early in your design. The tool uses Senté's Watt Watcher format, leveraging Watt Watcher library support and development tools. Peak Watcher supports logic, memories, I/Os, and virtual components. You use the tool to analyze a number of simulation patterns to get chip and module power-usage peaks during the simulation. Available for Unix platforms, the tool costs less than $40,000.

Taking on the sticky problem of implementing C-based algorithms in hardware, Frontier Design has two products to help automate algorithm conversion to bit-accurate RTL descriptions. The first products are the A/RT Library for development of fixed-point C algorithms and A/RT Builder for direct conversion of fixed-point C algorithms to VHDL or Verilog. The A/RT Library provides a set of C++ classes that contain fixed-point data-type and operator characteristics. The fixed-point classes model code in a bit-precise way, including overflow and quantization effects. A/RT Builder then converts the C algorithm to synthesizable RTL VHDL or Verilog. Frontier has optimized the conversion tool for Synopsys' (www.synopsys.com) Design Compiler, and Exemplar's (www.exemplar.com) Galileo and Leonardo synthesis tools. You can optimize your design with behavioral synthesis tools, including Mentor's (www.mentor.com) Monet or Synopsys' Behavioral Compiler. The A/RT Library is ready now for Unix and Windows; the library is free with an A/RT Builder purchase. A/RT Builder runs on Unix platforms and costs $20,000.

In addition to its IP-protection tool, VIP, Summit Design is also showing HDLScore, a tool combining finite-state-machine extraction and HDL-code coverage. You use the tool on behavioral-level, RTL, and gate-level Verilog code to determine as many as six types of coverage: block, path, and expression for Verilog code, and states, transitions, and state sequences for state machines. HDLScore provides text reports or graphical windows to view coverage results. Available now for Verilog simulators with standard APIs, the tool costs $22,000.

Cadence's Unix-based Affirma software products cover mixed-signal and level simulation--desirable capabilities for SOC designs. New Affirma tools include a coexecution simulator, based on Cadence's single-kernel Interleaved Native Compiled Architecture (INCA) technology, for running Verilog and VHDL simulations, and the NC VHDL simulator. You can also add Cadence's Cobra cycle-based simulator to the Affirma coexecution simulator to run mixed event-driven and cycle-based simulations. The complete Affirma system includes high-speed event and cycle-based simulation, full multilanguage de-bugging capabilities, and hierarchical block- or chip-level validation in a single coexecution environment. The system supports Verilog, VHDL, and C; behavioral-level, RTL, and gate-level simulation; event and cycle simulation; and digital and analog technology. (Cadence plans to add analog capability in 1999.) Prices for the new Affirma tools are $50,000 for the coexecution simulator and $25,000 for the NC VHDL simulator. For cycle-based simulation, add Cobra for $20,000, and, for Verilog simulation alone, get NC Verilog for $40,000.

For board-based systems, VeriBest's Expedition PCB tools address pc-board design. Expedition encompasses Ascent, Advance, and Pinnacle. You use these products for pc-board-design tasks from design-rule setting through batch routing. Ascent targets design of boards operating slower than 50 MHz. The tool offers full-rules capability; Gerber output; and no limits on the number of layers, components, or pin count. The Ascent starting price is $7500. Advance, for high-speed designs, adds automatic placement and routing, high-speed tuning control, and links to signal-integrity and thermal-analysis tools. Advance prices start at $18,000. Pinnacle adds differential-pair support and design-for-manufacturability constraints, integrates mechanical-design capability, in-cludes a Gerber reader, and supplies customized reports. Pinnacle's starting price is $36,000. All the Expedition tools run on Windows NT and include VeriBest's AutoActive technology, which combines automatic and interactive design.

Finally, Viewlogic has introduced Blast, a board-level static-timing analyzer. Using its Motive static-timing technology, Viewlogic developed Blast for analyzing single-board and multiboard systems. Tool features include a multiclock description language, elimination of certain types of false errors, a symbolic trace display, and transmission-line estimation. Blast can also read models that you import from some other timing-analysis tools, including Synopsys' PrimeTime. Blast prices start at $35,000.

--by Jim Lipman

Cadence Design Systems, San Jose, CA. 1-408-943-1234, fax 1-408-943-0513, www.cadence.com.

Escalade, Santa Clara, CA. 1-408-654-1600, fax 1-408-654-1616, www.escalade.com.

Frontier Design, Danville, CA. 1-925-648-2683, fax 1-925-648-2684, www.frontierd.com.

InfoQuick, Costa Mesa, CA. 1-714-631-2456, fax 1-714-966-2512, www.info-quick.com.

Pads Software, Marlborough, MA. 1-508-485-4300, fax 1-508-485-7171, www.pads.com.

Senté, Acton, MA. 1-978-635-9080, fax 1-978-635-9575, www.senteinc.com.

Simerica, San Carlos, CA. 1-650-592-6705, fax 1-650-592-6706, www.simerica.com.

Summit Design, Beaverton, OR. 1-503-643-9281, fax 1-503-646-4954, www.summit-design.com.

Synplicity, Sunnyvale, CA. 1-408-617-6000, fax 1-408-617-6001, www.synplicity.com.  

VeriBest, Boulder, CO. 1-303-581-2300, fax 1-303-581-9972, www.veribest.com.

Viewlogic Systems, Marlborough, MA. 1-508-480-0881, fax 1-508-480-0882, www.viewlogic.com.

Xynetix, Fishers, NY. 1-716-924-9303, fax 1-716-924-4729, www.xynetix.com.   

ADCs push bits and speed, cut power and size

Taking advantage of the low-pin-count potential of the serial interface, A/D-converter vendors are packing impressive specifications into eight-pin ICs. Burr-Brown, for example, has introduced the ADS7818, a 12-bit converter that offers 500k samples/ second and dissipates just 11 mW from a 5V supply and 2.5 mW in power-down mode. Typical SNR is ­78 dB for a 100-kHz input; worst-case SNR is ­72 dB. The device includes an internal 2.5V reference and a differential input, and it guarantees no missing codes over its 0 to 5V input range. The $5.60 (1000) IC is available in MSOPs and mini-DIPs.

At another point in the multidimensional-converter-performance matrix, the LTC1404 from Linear Technology Corp is a 12-bit, 600k-sample/second converter that operates from a 5V supply for 0 to 4.096V inputs or ±5V for ±2.048V inputs. The SO-8-packaged device requires 75 mW for operation and has a 60-µW sleep mode and a 7.5-mW nap mode. In nap mode, the device can perform conversion 350 nsec after awakening. The $5.10 (1000) converter guarantees no missing codes with typical 72-dB SNR and distortion and ­80-dB total harmonic distortion for 300-kHz input signals.

--by Bill Schweber

Burr-Brown Corp, Tucson, AZ. 1-520-746-1111, fax 520-746-7401, www.burr-brown.com. 

Linear Technology Corp, Milpitas, CA. 1-408-432-1900, fax 408-434-6441, www.linear-tech.com. 

Antifuse shift benefits synthesis

Hardware-description-language (HDL) Synthesis-based-design advocates tout time to completion and logic-reuse advantages over traditional, schematic methods. But HDLs depend on cheap logic gates and abundant, fast on-chip interconnections to overcome their inherent efficiency and performance shortcomings. Actel's new SX FPGAs address these shortcomings with a modified approach to antifuse technology.

In previous Actel products, the user-programmable antifuse switches coexisted with logic structures in the substrate, consuming precious die area. By moving the antifuses above the transistors--between the second and third layers of interconnecting metal lines--Actel can shrink the die for a given gate count. Actel's new antifuse approach also provides much lower impedance per switch, both raising performance and reducing power. Antifuse competitor and legal combatant QuickLogic (www.quicklogic.com) for several years has used a similar antifuse structure, ViaLink.

The SX "sea-of-modules" array contains C- and R-cell logic structures. C-cells comprise a two-level combinatorial multiplexer with four control signals and four data inputs, one of which you can optionally invert within the cell. R-cells include a flip-flop with flexible clocking and asynchronous preset and clear, as well as another two-level input multiplexer that selects from two routing networks or the flip-flop's fed-back output.

Actel combines C- and R-cells into Type 1 or Type 2 clusters. Type 1 clusters contain two C-cells and an R-cell, and Type 2 clusters include one C-cell and two R-cells. These clusters further combine into higher level SuperClusters. Two Type 1 clusters make up a Type 1 SuperCluster, and a Type 1 and Type 2 cluster combine to form a Type 2 SuperCluster. SX devices include many more Type 1 SuperClusters than Type 2 alternatives, and, if you do the math, you realize that this partitioning results in a high ratio of combinatorial logic to flip-flops.

Theoretically, SX devices should implement traditional complex-PLD decoding and state-machine functions more easily than do other more proportionally register-rich FPGAs. Conversely, designs with large amounts of synchronous datapath logic or that can take advantage of on-chip RAM, which SX FPGAs lack, may see better results with alternative FPGA architectures from Actel and other vendors. The estimated-16,000-gate A54SX16 with 176 I/O pins and 528 dedicated flip-flops is now available for $15.50 (50,000). The $8.90 A54SX08 and $27 A54SX32 will be available for sampling in the third quarter, and the $55 A54SX64 should appear early next year. The company's free HDL Coding Style Guide gives a number of useful suggestions for ensuring optimum synthesis results.

--by Brian Dipert

Actel Corp, San Jose, CA. 1-408-739-1010, fax 1-408-739-1540, www.actel.com.

Cell-phone RF amp juggles trade-offs to yield small package

Regardless of the cell-phone or personal-communications-service standard you adhere to, you still need an analog RF power amplifier for that final signal boost. Motorola's 1.9-GHz MRFIC1817 develops 32-dBm output power and 27-dB power gain from a 3.6V supply, making the device suitable for 1W DCS1800 cell phones and base-station drivers. The GaAs device come in a 16-lead power flatpack with an electrically grounded metal slug underneath. When you solder reflow to the pc board, this slug provides low-impedance electrical and thermal paths. Maximum dissipation of the $5.89 (10,000) device is 5W.

--by Bill Schweber

Motorola Semiconductor Products, Phoenix, AZ. http://motorola.com/sps.

Supply controller assuages processor power's split personality

Cherry Semiconductor's dual-channel, buck-switching CS-5127 controller IC helps you design µP CPUs that need both 3.3V I/O voltage and 2.8 to 5V core-voltage rails. By putting two semi-independent buck controllers in a 16-pin package, the device saves you from duplicating some internal functions, such as the programmable oscillator, and maintains disjoint operation for each output with a nonsynchronous design. Each controller output can supply dc current of 100 mA (500 mA maximum) to drive a MOSFET gate.

The $1.90 (1000) IC in-cludes a 5V internal reference and operates from 9.4 to 25V. It needs only one capacitor for loop compensation and has 100-nsec transient loop response because of its V² control topology. A pair of undervoltage lockouts built into the IC ensures that its outputs are off until both input and reference voltages reach acceptable minimum values; soft-start circuitry prevents output overshoot. If you need only one output, you can disable the second channel via an external control line to reduce power dissipation.

--by Bill Schweber

Cherry Semiconductor Corp, East Greenwich, RI. 1-401-885-3600; fax 1-401-885-5786, www.cherry-semi.com. 

IC connects ATM transceivers to telephony-based backplanes

The M590500 IC from Mitel Semiconductor works in asynchronous-transfer mode (ATM), the Adaptation Layer 1 (AAL1), and the segmentation-and-reassembly (SAR) layer. The IC simultaneously processes as many as 1024 bidirectional ATM virtual-channel connections to terminate 1024 full-duplex, 64-kbps voice channels. This device enables ATM edge switches, ATM access concentrators, and private branch exchanges to connect ATM to the time-division-multiplexed (TDM) environment of the Public Switched Telephone Network (PSTN). With the MT90500, designers can concentrate telephone connections originating from 42 T1 or 32 E1 TDM lines into one chip for ATM processing.

A selection of clock-recovery options allows flexibility for processing timing between legacy telephony-based TDM networks and ATM networks. The built-in clock state machines are suitable for systems that handle TDM clocks in ATM networks. The device's ATM connections are through Utopia Level 1 interfaces to standard ATM physical-layer devices. A second Utopia port lets you connect an AAL5 SAR processor for data communications or to cascade another MT90500, doubling the TDM voice-channel capacity. The TDM bus interface supports most standard telephony serial-data-stream buses at 2.048, 4.096, and 8.192 Mbps. The $150.45 (1000) MT90500 is available in 240-pin PQFPs.

Mitel also offers an evaluation kit with a tool set for hardware and software integration. The kit includes a system circuit design for a 155-Mbps ATM user-network interface. The kit also includes local TDM crosspoint switching functions, codec and analog transceivers, and a PLL for implementing TDM clock recovery from the ATM network connection. The kit costs $2695.

--by Stephen Kempainen

Mitel Semiconductor, Kanata, ON, Canada. 1-613-592-2122, fax 1-613-592-6909, www.semicon.mitel.com.  

Analog isolation amp deflects motor's hostility

The increasing use of processor-based motor controls highlights a key challenge in this application: You have to prepare for high common-mode voltages and grounding problems, often mandating that you use isolated analog channel. Hewlett-Packard designed the HPCL-788J amplifier IC for this application. It provides an optically isolated signal path between a sense resistor in the motor-phase winding and an A/D-converter input, transforming a nominal ±200-mV input into a full-scale output that ranges from 0V to the reference voltage value you provide (typically, 4 to 5V).

Isolation alone, though, does not make a motor-compatible channel. The HPCL-788J also provides a separate fault indication that responds in 3 µsec to a winding short circuit so you can protect driver transistors. You can "wire-OR" these faults for multiphase motors. In addition, you can use a "wire-ORable," rectified, absolute-value output to immediately measure the motor load, because this function performs polyphase rectification, yielding a dc signal representing rms motor current. Common-mode voltages in motor applications are not static, either, but can swing several hundred volts in a few nanoseconds, so the HPCL-788J tolerates transient common-mode-voltage slew rates as high as 10 kV/µsec. The $4.55 (1000), 16-lead SOIC meets or is waiting for numerous regulatory approvals, including UL, CSA, and VDE 0884.

--by Bill Schweber

Hewlett-Packard Co, Palo Alto, CA. www.hp.com/HP-COMP/isolator/hcpl788j.html.  

QED grabs Microsoft's support for WinCE

Last year, when MIPS (www.sgi.com/MIPS) announced Windows CE support for its processor cores, the company hard-coded many of the MIPS-specific features into the kernel. Partially through persuasion from Quantum Effect Design (QED), Microsoft (www.microsoft.com) has removed some of the hard-coded capabilities and replaced them with parametric features. For example, the translation-look-aside buffers (part of the MMU) was previously 32 entries; now, you can modify the number of entries. Another change is that you can configure the cache structure. The original WinCE implementation also did all floating-point operations using software emulation; it now supports both hardware floating-point and software emulation. Although Microsoft isn't up to doing any special favors for any company, it's enlightening to see that QED has done its part to get WinCE support for its processors. In the third quarter, Algorithmics (www.algor.co.uk) will also support QED with WinCE-capable development platforms that contain QED's RM52xx processors.

--by Markus Levy

Quantum Effect Design Inc, Santa Clara, CA. 1-408-565-0300, www.qedinc.com.

PC-board-design tool does preroute crosstalk analysis

LineSim XT from HyperLynx helps you analyze and predict crosstalk on pc boards before you start routing. The tool uses a boundary-element field solver to calculate coupling parameters on traces with complex routing, including cables and connectors. The tool lets you view electric- and magnetic-field lines for "crosstalk neighborhoods," local regions of adjacent board conductors. LineSim XT then generates a report of coupled matrix capacitances, inductances, impedances, and propagation velocities for each neighborhood. You use this information to determine differential impedances, where appropriate, on the pc board.

The simulator converts geometric crosstalk data between adjacent board conductors into electrical data, which you can see on a virtual oscilloscope display. In addition, LineSim XT recommends an optimal resistor termination array that you can use to eliminate differential and common-mode reflections on differential-signal line pairs. Using the tool's preroute crosstalk analysis features lets you eliminate potential electrical-coupling problems prior to board routing.

LineSim XT will be available in June on Windows 95- and NT-based platforms. Tool prices start at $6000. For $7495, you can get LineSim Pro, which couples LineSim XT with LineSim EMC, which you use for preroute electromagnetic-compliance analysis.

--by Jim Lipman

HyperLynx, Redmond, WA. 1-425-869-2320, fax 1-425-881-1008, www.hyperlynx.com.

Dust off logic and memory cobwebs

With 17 chapters, two appendices and more than 1000 pages, Application-Specific Integrated Circuits by Michael John Sebastian Smith (Addison-Wesley Publishing, 1997, ISBN 0-201-50022-1) is not a casual weekend read. However, its impressive breadth and depth of user-configurable logic coverage leave little doubt that it will satisfy almost any reader's thirst for knowledge. Smith, a professor at the University of Hawaii (Honolulu), begins with an eight-chapter review of ASIC and programmable-logic technology and device alternatives, CMOS-logic theory, and interconnection options. The next six chapters cover logical-design techniques, beginning with schematics and expanding to simple and then more complex hardware description languages. Smith discusses logic simulation, synthesis, and test coverage. He then turns his attention to mapping design netlists to physical-device architectures, including partitioning, placement, routing, and estimating performance and power consumption.

In another interesting book, Jim Handy, an analyst at Dataquest (www.dataquest.com), shows that his memory expertise extends far beyond forecasting how many chips will be sold in a year. His The Cache Memory Book (Academic Press, 1993, ISBN 0-12-322980-4) is updated in a second edition to reflect the four-year technology progression since first publication. Handy focuses on CPU caches and targets practicing engineers, not students, which means lots of practical advice, few equations, and no mind-numbing academic verbiage. His book applies not only to PC architects targeting x86 CPUs and Windows 98 or NT, but also to embedded designers with other µPs and software platforms.

The book provides a cache overview, discussing tags, the relationship between cache thrashing and software characteristics, and cache's impacts on bus traffic and power consumption. It also delves into simple statistics in explaining various cache trade-offs; logical versus physical, associativity, unified versus split, write posting, line length, memory-map partitioning and multistage complexity. Two chapters outline special considerations for RISC and multimaster systems, and another reveals unique cache techniques that various companies have implemented. A 24-pg glossary provides essential reference material.

--by Brian Dipert

Addison-Wesley, www.aw.com 

Academic Press, www.apnet.com 

Cahners gets a new logo

You may have noticed the new blue and orange funnel and the new Cahners logo on the cover. The logo is a symbol of our commitment to providing you with the technical information you need to make the right professional decisions, and the choice of colors should suggests an open, easy-to-work-with style. The funnel shape represents our efforts to distill and filter critical insight from the vast universe of data.

Passive-backplane CPU packs MPEG-1 decoder

Embedded-system designers can choose from a plethora of single-board computers, but few pack multimedia capabilities that match Teknor's PCI-934. The board hosts all Socket-7, Pentium-class processors at speeds as high as 233 MHz and integrates a 64-bit graphics accelerator and MPEG-1 video decoder. Teknor targets the multimedia board at sales and information kiosks, videoconferencing, and machine-vision applications. You can use the board in passive ISA or PCI Industrial Manufacturers Group-compliant PCI-ISA backplanes. It includes the usual lineup of I/O ports and peripherals and includes support for CompactFlash solid-state memory modules. A PCI-934 with a 166-MHz processor and no memory costs $2055.

--by Maury Wright

Teknor Industrial Computers, Boisbriand, PQ, Canada. 1-514-437-5682, www.teknor.com.

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