June 18, 1998

WHAT'S HOT IN THE DESIGN COMMUNITY

CompactFlash module pumps data rate to 1.4 Mbytes/second

CompactFlash has clearly become the miniature storage medium of choice for digital cameras and personal digital assistants, and companies are working to improve the performance of the technology. The industry group behind CompactFlash developed the technology to host flash memory that typically features slower memory-write cycles than those of other types of memory. The long write cycles impact end users, for example, by increasing the time they must wait between consecutive snapshots with a digital camera. Silicon Storage Technology attacks the CompactFlash performance problem from several angles. The company developed its own ATA controller and flash cell for optimum write performance. The controller includes dual 2k×8 static-RAM buffers for incoming data. The resulting SST family of CompactFlash cards can sustain data- transfer rates of 1.4 Mbytes/second, whereas the most widely available cards on the market today sustain rates of approximately 200 kbytes/second. The company offers modules in densities of 4 to 24 Mbytes with prices of $40 to $140 (1000).

--by Maury Wright

Silicon Storage Technology, Sunnyvale, CA. 1-408-735-9110, www.ssti.com.

Small UPS units wield big backup clout

Miniature uninterruptible power supplies from Guardian On Board Ltd come in three miniature form factors. The PowerCard is an internal UPS with self-contained NiCd batteries on a full-sized ISA or PCI PC card. It offers all-around power protection for a complete computer system--PC, monitor, peripheral equipment, and telephone/data lines. The PowerCard Split is an internal UPS on a half-sized card. A tether connects the external NiCd battery pack to the UPS. This UPS targets OEM custom development for use in bundling full-time UPS and surge-suppression functions in small PCs, retail point-of-sale terminals, or telephone systems. The PowerGuard is a mini external UPS that you can mount flat, upright, or on the wall.

All three models offer 420-VA (250W) backup capacity and spec 94% conversion efficiency during battery-backup periods. The output is a stepped-approximation sine wave, which appears two to four msec after a power failure. Backup times for half and full loads are 17 and 5 minutes, respectively, and 25 and 7 minutes for optional versions called "Pro," which use a NiMH battery pack instead of NiCd. The devices meet the stringent UL 1950 safety standard and exhibit only 2ºC temperature rise in backup mode. An intermittent audible beep warns users when the computer is in backup mode; approximately 2 minutes before full discharge of the UPS' battery pack, the beep changes to a continuous tone. The units come with software that provides automatic shutdown and furnishes updates about the system power supply and the UPS' operational status. $199 (estimated street price).

--by Bill Travis

Guardian On Board, Austin, TX. 1-512-236-0503, www.guardian-ups.com.

Digitally controlled potentiometer adds comparative twist

The versatile digital potentiometer, which replaces the traditional mechanical device with an electronically adjust-able, no-moving-parts version, can provide you with further benefits via IC integration. Xicor's X9440 and X9448 digitally controlled potentiometers add comparators to the basic re- sistor-string function, thus simplifying test and calibration applications when you need to match a signal against an ad-justable threshold.

The 64-tap devices have full-scale resistance of 10 kohm and operate from voltages as low as 2.7V; standby operating current is 1 µA. Available in 24-lead packages, each device contains two independent resistor strings, comparators, and latched outputs, with a common interface and a shared 128-bit EEPROM for nonvolatility. The X9440 has a 2-Mbps SPI digital port, and the X9448 incorporates a 400-kbps serial interface. The ICs cost $3.95 and $3.75 (10,000), respectively, in their SOIC-package versions.

--by Bill Schweber

Xicor Inc, Milpitas, CA. 1-408-546- 3534; fax 1-408-546-3534; www. xicor.com.

Multiaxis force sensor gravitates to custom designs

The Aurora multiaxis force Sensor, an EDN Innovation Finalist (EDN, Feb 2, 1998, pg 70), is now available in application-specific custom versions. The devices are solid ceramic, two- or three-axis sensors based on thick-film technology. They provide a linear output in all axes and have no moving or rubbing parts and, thus, no wear-out mechanism. Bokam has created a Custom Aurora Team to focus on product customization for applications using any volume from one to 60,000 pieces. Potential applications for the sensors include three-axis force-measurement systems, oscilloscope cursor control, medical-equipment motion control, MRI or ultrasound-system motion control, navigation-system cursor control, audio-visual equipment, and fly-by-wire systems. Prices range from $20 to $100, depending on the level of system integration, the custom configuration, and the quantity.

--by Bill Travis

Bokam Engineering, Santa Ana, CA. 1-714-513-2200, fax 1-714-513-2204, www.bokam.com.

RFID arena expands with rugged tags and 23-cm range

The diverse RF-identification (RFID) world includes an assembly of tags, readers, frequencies, protocols, and formats, each targeting the needs and constraints of various applications (see "RF, automatic ID references help you sort through choices," EDN, Feb 2, 1998, pg 22). Omron Electronics' V700 series of read/write systems and matching tags aims at applications requiring ruggedness at 200-mm distances for read/write operation and 230 mm for read-only functions. Operating at 125 kHz, this RFID system's tags store as much as 128 bytes in EEPROM with simultaneous, multiple-tag access.

Two coin-shaped tag styles are available. A $5 (OEM) style measures 20 mm in diameter and 2.5 mm thick at its center, operates at temperatures as high as 180ºC for 200 hours, and is submersible. You can use it in harsh environments, such as laundries and industrial washing machines. A 23-mm-diameter, 1.2-mm-thick tag targets more conventional environments, such as baggage tracking, access control, and pallet identification. The read/write head--the antenna--comes in a 250×200×35-mm focused version and a 650×200×35-mm version. Completing the system, the controller operates from a 24V-dc supply and has an RS-232C interface to your host computer; board-level readers and controllers will be available this year. Prices for this CE-, UL-, and FCC-approved system begin at $1500.

--by Bill Schweber

Omron Electronics Inc, South Schaumburg, IL. 1-847-843-7900, fax 1-847-843-7787, www.omron.com.

Products merge chip hardware and software design

To address the growing complexity of system-on-chip (SOC) design, three companies offer new or updated products for hardware/software design. Quickturn Design's Mercury verification system combines a new hardware platform with proprietary software for multilevel, multilanguage chip verification. With both simulation and emulation capabilities, Mercury lets you verify your chip from initial design partitioning through system-level integration. Significant features in Mercury include the SimServer mixed-level simulation engine; a multilevel memory architecture to handle various levels of design complexity; and IMPX, a unique custom-interconnect-chip architecture to quickly steer signals within Mercury.

SimServer combines both RISC µP and FPGA technology for verifying chips. Mercury achieves multilevel simulation by mapping a design-specific, event-driven simulation algorithm onto an FPGA array and letting the RISC chips do nonsynthesizable testbench, RTL, and behavioral simulation. The FPGA array then simulates the synthesizable portion of your design at a rate as much as 10,000 times faster than software-only event-driven simulation, according to Quickturn.

Mercury's three levels of memory include internal FPGA-chip SRAM; configurable memory chips on emulation boards within the Mercury chassis; and dedicated memory boards, also in the chassis. Each FPGA chip gives you 40 kbits of synchronous, multiported memory. The emulation-board-based memory has as much as 3 Mbytes/board with as many as 15 ports. Each dedicated memory board has 128 Mbytes, giving you 1 Gbyte of memory in the largest Mercury configuration.

The IMPX architecture combines FPGAs and custom-interconnect chips that function as signal crossbars. Letting the custom-interconnect chips handle Mercury's crossrouting, instead of giving the signal-routing job to the FPGA array, provides faster chip verification. IMPX lets you verify designs with as many as 32 independent clocks. You also can trade off emulation speed and capacity.

Mercury comes in two basic hardware configurations: The SE series, ranging from 500,000 to 2 million gates, and the E Series, spanning 1 million to 10 million gates. The lowest level configuration (500,000 gates) costs $395,000.

Based on its Vera hardware-verification language (HVL), Systems Science's new Vera-SV lets you create a virtual prototype of your chip. Vera-SV automatically generates functional tests that simulate a chip's target environment, including device drivers and application code. You use this prototype to verify chip hardware and software before you have a physical chip to test.

Vera-SV includes the basic Vera-HVL system along with software modules for hardware/software co-verification, automatic stimulus generation, and dynamic-coverage feedback. For co-verification, you model the chip in Verilog or VHDL and run the HDL code on a workstation or PC with driver, diagnostic, and application software. The stimulus-generation module provides random, constrained-random, conditional-random, and directed-functional tests to functionally verify your design. With dynamic coverage, you can use information Vera-SV gathers from running your testbench to guide follow-on test generation for improved speed and efficiency.

An additional Vera-SV feature is the tool's distributed-simulation capability, which lets you run complex verifications concurrently on multiple platforms by partitioning the top-level verification into independent subtasks. Vera-SV costs $12,500 to $32,500, depending on configuration, and runs on Unix and Windows NT platforms.

Finally, Synopsys has updated the Eagle hardware/software co-verification tools, which the company obtained when it merged with Viewlogic Systems (www.viewlogic.com). Version 3.2 Eagle adds an interface to Synopsys' Cyclone cycle-based simulator, which Synopsys claims provides simulation as fast as 5000 instructions per second. Eagle also has improved instruction-set simulator (ISS) support and works with 18 new µP models from Advanced RISC Machines (www.arm.com), Fujitsu (www.fujitsu.com), Hitachi (www.hitachi.com), IBM (www.ibm.com), LSI Logic (www.lsilogic.com), MIPS (www.mips.com), and Motorola (www.motorola.com). You can get Eagle for either Unix- or Windows NT-based operation for a $35,000 starting price.

--by Jim Lipman

Quickturn Design Systems, San Jose, CA. 1-408-914-6000, fax 1-408-914-6001, www.quickturn.com.

Systems Science, Palo Alto, CA. 1-650-812-1800, fax 1-650-812-1820, www.systems.com.

Synopsys, Mountain View, CA. 1-650-962-5000, fax 1-650-965-8637, www.synopsys.com.

Micromotherboard yields tiny,200-MHz MMX Pentium PC

The latest Pentium CardPC from Cell Computing targets applications for ruggedized tablets, wearable computers, portable test equipment, and medical instrumentation, among others. The P200 CardPC crams most functions of a standard motherboard into a 3.4×2.1×0.5- in. package. With the addition of an LCD screen, a keyboard, and memory, the CardPC runs standard Windows 95 and NT.

The ISA-compatible motherboard includes the 200-MHz Pentium processor with MMX technology and the Intel 430TX-system controller. You can install as much as 128 Mbytes of DRAM via a 144-pin DIMM socket. An onboard Trident (www.tridentmicro.com) Cyber9320 PCI graphics controller with 1 Mbyte of video RAM provides interfaces for LCD and CRT displays. National's (www.national. com) PC87334 Super I/O chip supports two serial ports, one parallel port, and FDD/IDE interfaces. A 236-pin, high-density EASI connector brings out all the I/O signals plus the ISA expansion bus.

Samples of the Pentium P200 CardPC are available immediately, and volume shipments will begin in the third quarter. The price is $899 (1000).

--by Warren Webb

Cell Computing Inc, San Jose, CA. 1-408-967-8800, fax 1-408-967-8801, www.cellcomputing.com.

Triple ADC focuses on RGB-to-LCD front end

The large installed base of analog RGB PC monitors and the need to support such monitors in future systems are impediments to replacing RGB monitors with LCD units. (Admittedly, LCD cost is another.) The requisite analog-to-digital conversion remains a challenge, although IC vendors are addressing the signal-transformation and image-space-transformation problem (see "IC forms center span of CRT-to-flat-panel-display bridge," EDN, May 21, 1998, pg 11). The AD-9483 from Analog Devices addresses the conversion problem by simplifying circuit designs. This triple 8-bit converter aims at digitizing RGB signals and supports display resolutions as high as 1280×1024 pixels at a 75-Hz refresh rate, compatible with SXGA LCD monitors.

The converter accepts three differential 1V pk-pk analog signals and encodes them at 140M samples/ sec; full-power bandwidth is 300 MHz. The IC is available in a 100-pin PQFP and includes a 2.5V reference and track/hold circuitry. You need provide only a clock and a 5V power supply, and you can power the three-state CMOS output buffers separately from 3.3V to reduce dissipation. The datapath from the converter to your system is via a single full-speed parallel channel or interleaved through dual output channels in demultiplexed mode, which halves the required port-clocking speed. The $25.50 (1000) converter requires less than 1.5W of power.

--by Bill Schweber

Analog Devices Inc, Norwood, MA. 1-781-937-1428, fax 1-781-821-4273, www.analog.com.

ASIC+FPGA=fast, wide PCI

Lucent Technologies, with its OR3TP12, becomes the second manufacturer to announce a product combining ASIC and programmable logic on one die ("ASIC and programmable logic join forces in new core approach," EDN, March 2, 1998, pg 20). The company begins with its 3.3V OR3T55 FPGA ("Budding FPGAs beat last year's crop," EDN, March 26, 1998, pg 18), replacing 72 programmable-logic cells (PLCs) with a 64-bit initiator/target PCI hard core implemented in gate-array ASIC and capable of zero-wait-state performance as fast as 66 MHz. The core also includes large on-chip read and write FIFO buffers of 2 kbits each for initiator configurations and 1 kbit each for targets.

The OR3TP12 retains 252 PLCs of user-programmable logic, which Lucent estimates supports a 30,000- to 60,000-gate design. By replacing 72 PLCs (7776 typical gates) with 85,000 gates of ASIC, the company claims to deliver logic complexity comparable with, performance higher than, and price less than half that of its OR3T125. Lucent's FPGA-based PCI core currently supports only 50-MHz operation with much smaller FIFO buffers and no 64-bit option. The OR3TP12, at $79.80 (25,000), is also only 10% more expensive than the OR3T55 on which it is based.

Lucent provides not only the ASIC-core netlist but also functional and timing models to enable you to simulate with the PCI-logic block in your preferred design environment, and the company's Foundry back-end tools treat the interface between FPGA and ASIC regions as a set of OR3T55 PICs (programmable interface cells). On-chip dedicated interfaces to PowerPC and i960 µPs make the OR3TP12 an interesting option for I²O designs. You can program the FPGA portion and customize options within the PCI core via a serial PROM, the µP interface, or the PCI bus using the default core settings. The OR3TP12 in 240-pin shrink QFP, 256-bump BGA, and 352-bump BGA packages will be available for sampling in August, and the company expects to begin production in the fourth quarter. Lucent claims that it already has a functional test chip.

--by Brian Dipert

Lucent Technologies, Allentown, PA. 1-610-712-4331, fax 1-610-712-4209, www.lucent.com.

Graphics controller increases embedded memory, widens on-chip bus

NeoMagic's MagicMedia256AV fifth-generation notebook PC graphics controller not only increases the amount of on-chip DRAM to 2.5 Mbytes, but also widens the interface between memory and logic from 128 to 256 bits ("Embedded memory: the all-purpose core," EDN, March 13, 1998, pg 34). The company also beefs up support for MPEG-2 motion-compensation decoding and integrates a SoundBlaster-compatible wavetable audio controller. The interface to the system north-bridge core logic is a standard 1X Advanced Graphics Port (AGP), which NeoMagic chose because it delivers a performance boost over PCI and to minimize power consumption versus a full 2X AGP sideband implementation.

By integrating the 2-D graphics and video frame buffers, digital-versatile-disk (DVD), and audio logic on chip, the company claims not only higher performance over the conventional multichip alternative but also a five-times decrease in power consumption, translating to more than 100 extra minutes of battery life, and a seven-times decrease in board space. The MagicMedia256AV can drive an LCD screen at resolutions as high as 1024×768 pixels with 24-bit color depth. The wide on-chip data bus between memory and logic delivers 3.2-Gbyte/second peak bandwidth.

Noticeably absent is any hardware support for 3-D graphics acceleration. NeoMagic claims that its OEM customers, which target their systems primarily at business users, prioritize 3-D-graphics performance below DVD, audio, and fast 2-D. The large on-chip DRAM arrays also leave less silicon available for logic than do less-power-sensitive desktop PC graphics chips. However, the company acknowledges that some business travelers not only crunch spreadsheets on airplanes and in hotel rooms, but also play an occasional game of Quake, so you'll probably see a faster AGP interface and hardware 3-D-acceleration in the not-too-distant future. Robust 3-D support will also be essential to enable the desktop-PC-replacement market. The MagicMedia256AV is currently available for sampling and will enter production in the third quarter. It costs $65 (10,000).

--by Brian Dipert

NeoMagic Corp, Santa Clara, CA. 1-408-988-7020, fax 1-408-988-7032, www.neomagic.com.

Don't even dream of getting this much current from an IC amplifier

Not all applications are low-power, low-current, or low-compliance. The Model 8100 from Clarke-Hess Communications Research is a precision, 100-kHz transconductance amplifier that supplies as much as 100A. The amplifier is stable with inductive and capacitive loads and offers output compliance as high as 7V. Applications for this system, which operates from 208 to 250V supplies and draws less than 11A, include testing broadband wattmeters, shunts, and current transformers. You supply a 0 to 2V input to drive the output current to full-scale range with six overlapping ranges (2, 20, and 200 mA and 2, 20, and 100A). Typical full-scale distortion for this $19,500 amplifier is less than ­60 dB to 20 kHz, ­50 dB to 50 kHz, and ­40 dB to 100 kHz. DC accuracy is 0.04%, and ac accuracy is 0.10%.

The front panel of the dc-coupled Model 8100 shows the input frequency and output compliance voltage; this voltage indicates the amount of series resistance in the load. In addition, you can both control and read the unit via its built-in IEEE-488-2 interface. Don't worry: If you need more than 100A output, you can connect the outputs of multiple Model 8100s in parallel.

--by Bill Schweber

Clarke-Hess Communications Research Corp, New York, NY. 1-212-255-2940, fax 1-212-691-8158, www.clarke-hess.com.

IEEE 1394 link- and physical-layer chips perform at 400 Mbps

Four link-layer chips from Texas Instruments and a three-port physical-layer (PHY) device from Lucent Technologies are now available for the 400-Mbps data rates in the IEEE 1394 FireWire serial-bus standard. TI adds the link-layer products to a family of IEEE 1394 interface devices that include link- and physical-layer devices. The new devices add or enhance features for efficient operation at 400 Mbps and provide better support for asynchronous data transmissions.

The GP2Lynx for general-purpose-PC and peripheral-equipment applications targets PCI-bus-to-1394 applications. The GP2Lynx increases the transmitting and receiving FIFO buffers to 2 kbytes each and includes a new data-mover port, enabling both asynchronous and isochronous transmissions. The PCILynx2 also has a 4-kbyte FIFO buffer and includes native Microsoft Windows 98 drivers that are backward-compatible with the first PCILynx device. The GP2Lynx will be available in the third quarter and cost $6 (1000). The PCILynx2 is available now and costs $11.32 (1000).

The DVLynx controller targets digital-video consumer-electronics applications, such as camcorders, videocassette recorders, and set-top boxes for cable TV. The device automatically parses digital-video data and non-digital-video isochronous data into 1394 packets. This parsing offloads the processing from the system processor. The DVLynx transfers data at only 200 Mbps but includes an 8-kbyte FIFO buffer and a bulky-data interface that allows for full bidirectional digital-video-data transfers or simultaneous digital-video and isochronous data transfers. The DVLynx will be available in the third quarter and cost $13.49 (1000).

The TSB12LV01 targets networking and computing systems with its 32-bit host-controller interface and flexible FIFO architecture, which allows various-sized packets for isochronous and asynchronous communications. This device, like all the new devices, is available in 100-pin TQFPs and sells for $8.10 (1000).

Both of TI's GP2Lynx and the PCILynx2 controllers claim compliance with the newest version of the 1394 specification, IEEE P1394a, even though the standard is now in the negative-ballot resolution stage and months from authorization. The balloting version of P1394a includes improvements for PC applications, such as power management, arbitration enhancements, and bandwidth optimization. In addition, this supplement to the standard specifies a four-pin version of the cables and connectors, standardizes the PHYchip to a link-chip interface, and corrects miscellaneous errors in the IEEE 1394-1995 original version of the FireWire standard.

Lucent's FW803 three-port PHY device also claims compliance with the P1394a specification and is the first of several 1394a devices from Lucent. The FW803 supports the 400-Mbps rate and dissipates less than 0.6W during normal operation. This low power dissipation allows the use of a 64-pin TQFP to house the device; competing vendors promote a larger, 80-pin package for their equivalent PHY devices. Software control further conserves power by individually putting any of the three ports into low-power mode. The FW803 is now available for sampling and costs $5 (10,000).

--by Stephen Kempainen

Lucent Microelectronics, Murray Hill, NJ. 1-800-372-2447, fax 1-610-712-4106, www.lucent.com/micro/ 1394/.

Texas Instruments, Dallas, TX. 1-800-477-8924, ext 4500, www.ti.com/sc/1394.

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