July 16, 1998

Board-level signal-integrity analysis: Sooner is better

Jim Lipman, Technical Editor

Higher chip complexity begets more complex pc boards. As chip designers place larger amounts of high-speed logic on chips, board designers face more problems. Additional board layers, denser board layouts, and tighter design constraints make it difficult for designers to develop new system-on-chip (SOC) designs. Foremost among these problems is getting a handle on board-level signal-integrity (SI) issues.

The tried-and-true way of analyzing a board prototype to see whether the design has met SI requirements is no longer feasible for many engineers. Shrinking design cycles and tight budgets often do not allow for board redesigns if you discover a problem at the prototype stage. Postlayout SI analysis helps save time and money during board debugging, but it may still be too late in the design cycle to solve an SI problem. The solution is a class of EDA tools that lets you do preroute SI analysis and use the analysis results to guide board place-and-route (P&R) operations. Combining the right preroute SI tools with your board-design experience minimizes the chance of finding an SI problem further down the design chain.

SI fundamentals revisited

"Signal integrity" refers to the quality of a signal on a line. Poor SI manifests itself not as a single factor, but as a combination of factors you need to recognize when designing your boards. A short summary of the most prevalent SI problems--reflection, ringing, ground bounce, and crosstalk--will help you understand what EDA-tool capabilities you need to have for both prelayout and postlayout board analysis.

Source and load mismatch causes trace reflections. An unmatched load reflects voltage back to the source. The reflected voltage is negative if the load impedance is less than the source impedance and positive if it is greater. Factors such as changes in trace geometries, incorrect trace terminations, transitions through connectors, and power-plane discontinuities cause these types of reflections.

Signal ringing or rounding results from excessive inductance (ringing) or capacitance (rounding) on a trace. You may know ringing as an underdamped condition and rounding as an overdamped condition. You generally see these SI problems on periodic signals, such as clocks, and ringing and rounding result from many of the same factors as does reflection. You can minimize--but not eliminate--ringing with proper line termination.

Ground bounce results when a current surge occurs in a circuit, such as when a number of chip outputs switch simultaneously. When the chip's drivers switch, large transient currents go through the chip's package and the board's power grid. Inductance and resistance of the package and power grid create power-supply noise, causing a fluctuation in supply voltage and a voltage variation in the ground plane from true 0V (Reference 1). This noise, in the form of ringing, can adversely affect other switching components (Figure 1). Ground bounce increases with increased load capacitance, decreased load resistance, increased ground inductance, and increased number of simultaneously switching devices.

Whereas SI problems, such as ringing and ground bounce, are single signal-trace phenomena (along with the ground-plane return path), crosstalk results from the interaction of two signal-board traces and the ground plane, a so-called three-wire system. Crosstalk results from coupling between one trace causing the problem (the aggressor trace) and another trace in which the aggressor introduces the crosstalk problem (the victim trace). Mutual capacitance and mutual inductance between the aggressor and victim result in noise being induced in the victim from the aggressor. Capacitive coupling results in aggressor voltages coupling currents into victims; inductive coupling results in victim voltages from aggressor currents. Physical pc-board substrate parameters; spacing between board traces; and the electrical characteristics of the drivers, receivers, and trace terminations all affect crosstalk.

Crosstalk analysis is not as simple as determining distance between traces and calculating induced voltage in one trace from the other. Crosstalk amplitude depends not only on trace separation, but also on factors such as signal direction (the same or opposite in both traces) and the location of closest parallelism between victim and aggressor (near the driver, near the receiver, or between the driver and the receiver). Crosstalk increases with decreased trace separation, increased trace coupling length, faster driver edge rates, and improper line termination.

Preroute and postroute analysis

Analyzing and discovering SI problems on a placed and routed pc board are like discovering bad electrical wiring in a new house. In either case, the problem, which the designer (or electrician) might have found before completion of physical design, is now expensive and time-consuming to fix. Shrinking design times have all but eliminated waiting until pc-board prototyping to first look for SI difficulties. Using EDA tools to locate and analyze SI problems on a physically designed but not prototyped board eliminates the cost and time involved in making the prototype. However, if you find a problem at this stage of the design, the effort involved in board redesign and a new P&R operation still consumes engineering time and money. The solution is to use engineering knowledge and good analysis tools up-front, during initial board design, and before P&R to locate potential SI problems.

With tools for preroute board analysis, you need to have a design methodology that uses design constraints to place components on and to route between the components on the board. You determine--before physical implementation--the maximum allowable levels of SI-induced voltages on critical lines and design the pc board so as not to exceed these levels. Constraint-driven SI design is similar to but more complex than constraint-driven timing design because SI issues are more involved than timing delays from point to point on a board. An additional problem in constraint-driven SI design is that the number of board nets that are critical is constantly increasing. Often, more than half of the nets on today's high-speed boards are design-critical. Besides spotting potential SI problems, preroute analysis can help you select components, plan board-clock networks, and determine critical-net terminations (Figure 2).

Postroute SI-analysis tools give you more accurate results than preroute tools because postroute tools use extracted data from the physical layout rather than estimated data or models. You analyze routed boards to look for SI and other constraint violations and to verify layout correctness. If you do a good job on your preroute analysis and design, then you minimize the number and degree of postroute SI troubles. Even with a good preroute design, you should always do a thorough postroute SI analysis. You may have missed a problem, or you may discover one that is difficult to detect before physical layout.

One example of a difficult problem to spot before board routing is ground bounce. Some amount of bounce is always present because of power and ground inductance and resistance. Unfortunately, large, complex power and ground grids that may contain split planes, multilayers, and multiple apertures and gaps exacerbate the problem. You can't accurately model this level of physical complexity in a preroute design phase.To determine possible ground-bounce problems, use a tool such as ApsimOmni from Applied Simulation or AC/Grade from Viewlogic to analyze ground and power planes (Figure 3). ApsimOmni uses a shaped-base router and special field solvers to convert complex ground and power planes into models that other Applied Simulation Technology simulation tools can use. AC/grade employs 3-D analysis techniques to synthesize an equivalent circuit of multilayer power and ground structures. You can then use Viewlogic's XTK to do an SI analysis of the effects of these structures. Crosstalk analysis is also more accurate after board P&R.

A postroute crosstalk-analysis tool starts extracting the board's topology from a layout file. A field analysis, usually 2-D, follows to calculate the impedance, propagation velocity, and coupling magnitude of the traces. The tool then uses a transmission-line analysis to calculate crosstalk voltages on coupled traces. Analysis software usually works with IBIS (Input/Output Buffer Information Specification) or other behavioral models of trace drivers and receivers when looking for crosstalk and other SI problems, because Spice-level models are too slow for reasonable simulation runtimes (see sidebar "IBIS models: the foundation of good SI analysis"). These analysis tools use time-domain calculations to obtain SI parameters. If you need electromagnetic-compliance (EMC) calculations as well, EMC-analysis tools often do the same calculations through transmission-line analysis and then employ frequency-domain analysis to obtain E- and H-field emissions.

Available tools for SI analysis and simulation, both preroute and postroute, have wide variations in capability (Table 1). Some tools do single-trace SI analysis, whereas others have coupled-trace (crosstalk) capabilities. You use some tools only to analyze board traces, which depend on physical-design constraints you enter into the tool. Of these board-only tools, several have limited capacity with respect to the number of board layers, mounted components, and other board-design parameters. Unfortunately, board-only analysis tools limit your ability to accurately assess SI issues throughout a system. SI analysis depends not only on signal-flow simulation on a pc board, but also on other system components, such as board-mounted components, connectors, cables, and the interfaces between all these components.

System-level SI tools

SI-analysis tools for system-level evaluation look beyond a single pc board. These tools analyze system components, such as multiple boards, connectors, cables, and chip packages. Generally available as tool suites, system-level SI tools often include IBIS-interface capability for driver and receiver models, 2-D simulation of transmission lines for crosstalk analysis, a circuit simulator, and graphical displays of SI-analysis results (Figure 4). Some suites also have design advisers to help you correct a potential SI problem and multidomain-analysis capability.

Tools that do analyses in multiple design domains--electrical, EMC, thermal, and mechanical--have the advantage of doing truer system-level design. Changes you make to correct a problem in one domain may introduce a problem in another domain. For example, moving two traces farther apart to correct an SI problem may increase electromagnetic radiation beyond an acceptable limit or increase board size. Having a tool suite that lets you look at the effects of design modifications in different domains helps you converge on a design that meets all design constraints, not just those involved with SI and delay factors. Following are some examples of available tool suites for system-level SI-constrained design, including electrical-only and multidomain.

Ampredictor from Amp is a suite of SI-simulation and -interface tools for prelayout pc-board analysis. The suite has a net-topology editor, including direct linkage to the company's Ampredictor circuit simulator. A graphical user interface for the circuit simulator provides a "virtual oscilloscope," which simplifies measuring rise and fall times, delays, overshoot, undershoot, and crosstalk effects. Ampredictor also includes a 2-D field solver for lossy transmission-line models of pc boards and the Connector Noise Analyzer to analyze connector-induced noise.

Connector Noise Analyzer lets you select a connector; terminate its pins; and simulate critical parameters, such as crosstalk, phase shift, and ground bounce. You get models of Amp's own connectors with Ampredictor, but you can add your own models of other vendors' connectors. In addition, the product provides an IBIS-to-AmpSpice (Amp's version of Spice) converter to add drivers and receivers to your simulations. All Ampredictor's tools operate from a schematiclike net-topology editor, from which you generate an AmpSpice simulation of a multiboard critical net, including drivers, boards, connectors, cables, receivers, and a backplane.

Mentor Graphics used its acquired Interconnectix technology to develop a suite of tools for timing- and SI-constraint-driven pc-board floorplanning, placement, and routing tools. The Interconnectix tools use electrical-rule constraints without first translating them to a physical-rule set to guide floorplanning and physical board layout. Tool features include what-if design creation and modification within the tool suite, including the ability to add drivers, receivers, and nets for prelayout analysis. The Interconnectix tools also accept minimum, maximum, and typical IBIS-model data, letting you manually select and run corner cases during analysis. The tools have a 1-psec analysis resolution and support IBIS pin-level overshoot and undershoot. The Interconnectix tools interface with many third-party pc-board-layout tools, including those from Cadence, Pads Software (www.pads.com), and Zuken-Redac.

EDANavigator 3.0, Xynetix's virtual prototyping system, has an adviser backplane for including third-party analysis tools in a multidomain mode, using electrical, thermal, EMC, and board-assembly constraints. These tools provide design advisers, which tell you whether a design choice you make might present a problem for a postlayout design. Xynetix's System Engineer includes basic advisers for board form-factor, routability, and electrical-design decisions. Optional Xynetix design advisers for other design constraints are available at additional cost. Also, Design Advisor interfaces to many well-known SI and EMC tools are available from other vendors. Another Xynetix tool that plays with EDANavigator is Net Explorer. You use Net Explorer for defining net topologies and analyzing SI. You can view a net, add branch points and termination resistors, let Net Explorer extract data, and then set up and run third-party analysis tools. Net Explorer includes a pc-board layer-stackup editor and a constraint manager.

Cadence's SpecctraQuest uses shape-based-routing technology to bring together a suite of physical prototyping tools, including the Specctra shape-based router and a timing-driven bus designer with enhanced interconnect modeling. SpecctraQuest evolved from Cadence's BoardQuest. You use the suite to accurately characterize buses with a template-based approach. You view simulation waveforms in Cadence's SigWave viewer and can store bus models for reuse in other designs. You define I/O cell timing parameters and import timing information from Cadence's Verilog XL and static-timing analysis tools, including Synopsys' (www.synopsys.com) Motive. SpecctraQuest can also use packaging parameters, such as wire-bond and lead-frame parasitics, in a bus simulation.

Bundling schematic entry, model libraries, frequency- and time-domain simulators, and a Spice model generator, HP-EEsof's Picosecond Interconnect modeling suite provides pc-board, multichip-module (MCM), chip-package, and chip-modeling capabilities. The model libraries include multilayer coupled line and IBIS models. Using the modeling suite, you choose a modeling technique, enter physical characteristics (dimensions and materials) for the structure you're modeling, run a frequency-domain characterization, and generate a Spice model of the structure. Adding IBIS-model drivers and receivers lets you generate models of crosstalk, ringing, and other SI phenomena.

Chip-package analysis

Chip packages create particularly difficult SI-analysis problems. BGA and other SOC packages can have more than 1000 pins. These pins couple with intrinsic package inductances to give you serious crosstalk and ground-bounce problems if you neglect package contributions to SI analyses. The complexity of package contributions to these problems means you need some serious EDA-tool assistance to analyze the package (Figure 5).

Fortunately, EDA vendors offer some help in the form of package-analysis tools. Pacific Numerix offers PCB/MCM SI for board- and package-level, preroute and postroute SI analysis. The company also offers Turbo Package Analyzer for IC-package analysis. Both tools use parameter extraction that combines 2- and 3-D extraction techniques to get accurate estimates of package electrical parameters. Cadence's Advanced Packaging Ensemble can help in determining potential ground-bounce and other SI problems. This new tool combines chip-package layout and integrated chip-package and board analysis. The combination automatically generates package and power/ground-plane models and works with Cadence's SpecctraQuest to help you determine the effects of simultaneously switching outputs on package-board combinations. Xynetix's Encore BGA, a physical-design tool for BGA packages, works with third-party EDA tools for SI analysis.

Having good EDA tools for preroute SI analysis and virtual pc-board prototyping is not a complete solution. A simulation is only as good as the models it uses, and models of complex pc-board structures, surface-mount components, cables, and connectors are far from perfect. Like any other early electronic-system simulation, the results you get are less accurate than measurements on a fully loaded pc board. Use your preroute SI analysis to guide your design, and be sure to rerun analyses throughout and after completion of physical-board implementation. Finish off with measurements on a prototype board, which you need to check EMC anyway to verify design correctness (Reference 2).

IBIS models: The foundation of good SI analysis

Trying to find board-level signal-integrity (SI) problems before a real prototype exists is like building a house on quicksand: It doesn't work. You need accurate models for successful SI analysis. Most SI-analysis tools do a good job of modeling your pc board as a function of board materials and geometry. However, getting good models of what lies on and connects to the board, namely board components, connectors, and cables, is relatively difficult. IBIS (Input/Output Buffer Information Specification) models assist board designers in obtaining accurate information for SI-constrained designs.

IBIS behavioral models come from device current-voltage characteristics, rise- and fall-time data, and package information at a pin-to-pin level of detail (Reference A). Behavioral models protect vendor intellectual property (by supplying no internal details about the model) and run faster than do Spice models (thus giving you higher circuit-simulation capacity). They also are finding wide acceptance among EDA companies, board designers, and chip vendors. IBIS models can also account for many nonlinear aspects of an I/O buffer's design, such as electrostatic-discharge (ESD), forward-diode effects, and pullup and pulldown characteristics (Reference B).

Board designers use different versions of an IBIS model to check performance parameters. You use IBIS slow models with minimum currents and maximum signal-ramp times to model maximum delay times on the board. To determine SI parameters, such as overshoot, undershoot, and crosstalk, you use a fast model with maximum currents and the fastest signal-ramp times. See Reference C for an EDN article that gives additional IBIS-modeling details.

Both Hyperlynx and Cadence offer software to help you develop your own IBIS models. Hyperlynx's system is free if you're a semiconductor-company model developer and if the IBIS models you develop are free to the design public. The Windows-based development system includes a visual editor for creating, maintaining, and syntax-checking IBIS models; a transmission-line simulator for testing models under real-life loading conditions; other utilities to speed model creation; and IBIS application notes. You can get a free Spice-to-IBIS- converter from Cadence's Web page. Cadence also has an IBIS-modeling service to develop IBIS models from I/O Spice files and component databases. Remember to request IBIS models from your chip vendors if you plan to use IBIS modeling for your design's SI compliance.

References

A. Powell, Jon, and Chuck Berman, "Creating Behavioral Signal Integrity Models from Physical Measurements," DesignCon'98 High-Performance System Design Conference Proceedings, Jan 27 to 29, 1998, pg 91.

B. Lipman, Jim, "EDA tools accelerate high-speed pc-board design," EDN, March 28, 1996, pg 87.

C. Duehren, Derrick, Will Hobbs, Arpad Muranyi, and Robin Rosenbaum, "I/O-buffer modeling spec simplifies simulation for high-speed systems," EDN, March 16, 1995, pg 65.

References

1. Yuan, Frank, "Analysis of power/ground noises and decoupling capacitors in printed circuit board systems," 1997 IEEE Symposium on Electromagnetic Compatibility, Aug 18, 1997, pg 425.
2. Lipman, Jim, "Tools and techniques stifle EM emissions," EDN, Nov 6, 1997, pg 83.
3. Hartley, Rick, "Control of EMC and crosstalk at the pc board level," 1998 PCB Design Conference West Proceedings, March 23 to 27, 1998, pg 59.
4. Brooks, Douglas, "Circuit noise and EMI control," 1998 PCB Design Conference West Proceedings, March 23 to 27, 1998, pg 343.
5. Hillebrand, Friedbert, "Planning and implementing signal integrity within PCBs," 1997 PCB Design Conference West Proceedings, March 17 to 21, 1997, pg 315.
6. Harris, Stan, David Helster, John Lockwood, and Russell Moser, "Signal integrity analysis," Printed Circuit Design, Sept 1997, pg 30.

Jim Lipman, Technical Editor

You can reach Technical Editor Jim Lipman at 1-925-606-1370, fax 1-925-606-1563, ednlipman@mcimail.com.

You can reach Contributing Technical Editor David Marsh at +44 0 1953 789619, fax +44 0 1953 789619, forncett@compuserve.com.

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