September 1, 1998

Transistor quickly wakes sleeping LDO

Christophe Basso, Motorola Semiconductor, Toulouse, France

Portable systems, such as telephone handsets, make extensive use of low-dropout (LDO) regulators. These components provide noise-sensitive parts with a stable power-supply line. When a telephone enters standby mode, most of the circuits go to sleep by disabling the LDO's outputs. Operating current thus drops to a minimal level. When a user starts to dial a number, the LDO receives an enable signal and immediately delivers the nominal operating voltage. Unfortunately, most low-noise LDOs use a bypass capacitor that briefly loads the internal reference voltage upon wake-up. In fact, the output exhibits a latency period before reaching its steady-state level. With a 10-nF bypass capacitor, this period typically lasts 1 msec and correspondingly degrades the overall response time. The ultra-low-noise MC33263 from Motorola (www.motorola.com) also uses a 10-nF bypass capacitor. However, the EZCap architecture of the IC allows the use of an inexpensive decoupling capacitor (ESR from 10 mOhm to 3 Ohm) and allows the designer to speed the wakeup time (Figure 1).

The base of a low-cost pnp transistor connects to an RC network. At power-up, C₄ discharges. When the control logic sends its high-going wake-up signal, the transistor's base is momentarily tied to ground. The transistor turns on and immediately charges bypass capacitor C₁ toward its nominal operating voltage. After a few microseconds, the pnp turns off and becomes transparent to the regulator. This circuit dramatically improves the response time of the regulator from 1 msec to 30 msec (Figure 2). You need only adjust the RC time constant to avoid any bypass-capacitor overload during the wake-up transient. Such an overload would generate an unacceptable output overshoot. Because the transistor connects to the bypass pin, it does not degrade the noise performance of the LDO. (DI #2241)

Circuits provide 4- to 20-mA PWM control

Tom Gay, Darmstadt, Germany

The circuits in Figure 1 and Figure 3 are useful when you use 4- to 20-mA current-loop signals to control a PWM signal. In both circuits, the minimum pulse width (corresponding to a 4-mA loop current) and the maximum pulse width (corresponding to a 20-mA loop current) are independently adjustable in the dedicated application with the use of one reference voltage. Furthermore, the circuits shut down the PWM output signal in case of a loop break. Both circuits are low-cost; you can use any op amp that provides an adequate slew rate to handle the desired PWM frequency.

The PWM circuit in Figure 1 uses free-running oscillation. Amplifier IC₁ is a noninverting integrator that forces a constant current, I_C, into C₁, thus providing a constant linear slope on its output, V_PWM. When the divided fraction of V_PWM reaches the level of V_C on the negative input of comparator IC₃, the comparator's output switches high. Hence, FET Q₂ short-circuits divider resistor R₅, and the undivided level of V_PWM undergoes comparison with V_C. R₇ extends the turn-on time of Q₁ with respect to Q₂, such that FET Q₁ discharges C₁ with minimum delay. The output of amplifier IC₁, V_PWM, then rapidly slews down to the level of V_R4.

Consequently, the output of comparator IC₃ switches back to logic low, and IC₁ restarts charging C₁. To ensure that IC₃ returns to a logic-low level, you must generally set V_C a few millivolts higher than V_R4. The divider network, R₂, R₃, and R₄, guarantee this setting. You can use the output of comparator IC₃ as a trigger signal for synchronizing other circuits. Resistor R_IN terminates the loop current, and comparator IC₂ provides the PWM circuit's output signal, PWM_OUT, by comparing the current-loop signal V_IN with V_PWM. The circuit in Figure 1 has PWM_OUT set to 0% duty cycle at 4-mA loop current and 80% at 20-mA loop current (Figure 2).

The circuit in Figure 3 is a simplified, gated version of the circuit in Figure 1, with a synchronization input. It works the same, with one difference: The output of amplifier IC₁, V_PWM, rises to and remains at the positive supply rail for IC₁. As before, FET Q₁ short-circuits C₁ with each rising edge on the Sync input, causing IC₁ to slew V_PWM down to the level of V_R4. The network comprising R₂, R₅, and C₂ transforms a low-to-high transition on the Sync input into a narrow gate pulse, which turns on Q₁ for a short time. If you connect the Sync output of the circuit in Figure 1 to the Sync input of the circuit in Figure 3, you can omit R₂, R₅, and C₂. The following formulas apply to Figure 1:

These equations apply to Figure 3:

(DI #2242)

Circuit uses simple LED for near-IR light

Lukasz Sliwczynski, Marcin Lipinski, Institute of Electronics, Krakow, Poland

You can successfully use LEDs as sources of near-infrared light. However, when you need a source of light with precisely controlled power, a feedback loop is necessary to compensate for the temporal and thermal changes of the LED parameters. Standard LED types come with neither these monitoring detectors nor an external monitoring photodiode to detect part of the emitted light and generate a feedback signal. The situation calls for some mechanical fixture to mount the photodiode. Such a solution, however, is bulky and cumbersome, especially when space is scarce. You can solve the problem by using an 880-nm IPL10530KAL hybrid detector/emitter module from Integrated Photomatrix Ltd. A modulated IR light source uses only one dual op amp, a transistor, and two voltage regulators (Figure 1).

The modulation input acts as a reference voltage and connects via amplifier IC_1A to the comparing feedback-loop amplifier, IC_1B. The resulting output voltage drives the output transistor, Q₁, which directly drives the LED. Resistor R_E limits the maximum drive current to approximately 80 mA, thus preventing damage to the LED. You can reduce R_E's value if you need higher power levels; the absolute maximum rating for the LED is 500 mA. If you change R_E, you may need to alter the frequency-compensation network. The network comprises R_C and C_C and introduces a pole at 0 Hz and a zero at 1/2pR_CC_C into the open-loop transfer function. The zero cancels the pole (at approximately 100 kHz) that the monitoring-photodiode preamplifier introduces, so the pole is a dominant pole in the feedback loop.

With the component values shown, the 3-dB modulation bandwidth of the source is approximately 40 kHz. You can experimentally determine the value of the compensating capacitor, C_C by observing the voltage at Pin 3 of IC₂ and driving the circuit with a square wave (Figure 2). The output is a filtered version of the optical-output waveform. A Spice simulation shows the phase margin to be approximately 858. The AD822 dual rail-to-rail op amp accommodates modulation-input voltage from 0 to 5V. The slope efficiency of the entire source (defined as dP_l/dV_MOD) is approximately 1.5 mW/V and may vary slightly from unit to unit of detector/emitter modules.

You can use this design as an IR light source in a precise reflectrometric measurement system incorporating pulse modulation and synchronous detection. To increase accuracy of the system comprising the entire optical head, you can install the system in a thermally stabilized environment with temperature controlled to within 0.5°C. The long-term measured power stability of the source is better than 1 ppm after initial warm-up. (DI #2243)

Two-DAC circuit adds and subtracts

V Manoharan, Naval Physical and Oceanographic Laboratory, Kochi, India

A typical way to add two binary words and provide an analog output is to use several digital ICs that drive a DAC. The circuit in Figure 1 eliminates the use of several digital-IC packages and, hence, the need for the digital power supply. The circuit simultaneously carries out addition and subtraction on two 8-bit binary words and presents the output in bipolar analog form.

The hardware consists of four ICs, and the operation takes only 85 nsec, which is the settling time of the DACs plus the settling time of the op amp. IC₁, a precision 10V reference, provides the reference current for both multiplying DACs: IC₂ and IC₃. For these DACs, I_REFA=10V/R₁, and I_REFB=10V/R₂. In this case, I_REFA=I_REFB=I_REF=2 mA.

The output currents, I_OA and I_OB, depend on the respective A and B binary inputs and the input reference currents as follows:

where n is the number of input bits and N_A and N_B range in value from 0 to 2ⁿ-1, in accordance with the input binary words.

The DAC-08 has complementary current outputs. Therefore, you can express the complements of I_OA and I_OB as

where I_FS, the full-scale current of the DAC, is

The circuit configures IC_4B as a current-to-voltage converter. Thus,

Substituting I_OA and I_OB from Equations 1 and 2 into Equation 6 yields

IC_4A serves as both a current-to-voltage converter for I_OB and a buffer to the potential drop across R₃ because of the flow of I_OA. Thus, assuming R₃=R₄,

Substituting I_OA and I_OB from Equations 3 and 4 into Equation 8 and assuming that R₄=R₅ result in

(DI #2226)

Calibration technique uses sound

Aubrey Kagan, Weidmuller Ltd, Markham, ON, Canada

A number of Weidmuller Ltd's (www.weidmuller.com) products require output calibration for zero and span. Normally, a technician calibrates a product by monitoring a digital readout and adjusting the zero and span potentiometers in turn. Because the technician must concentrate so heavily on the readout, the technician often experiences eyestrain, and the screwdriver often slips from the potentiometer. You can use an ADC card to implement the calibration function on a PC, and you can add an audio feature to simplify the calibration. In some cases, the use of audio can replace the need for a digital readout.

The audio spectrum arbitrarily divides into two sections: The first section ranges from 100 to 500 Hz; the second is 1 kHz and higher. The method compares the measured value from the device under test (DUT) with the desired value. If the measured value is lower than the desired value, the output is a frequency from the lower range. Conversely, if the measured value is higher than the desired value, the result is a frequency from the higher range. The further away the measured value is from the desired value, the lower or higher in frequency the audio signal becomes. The object is to adjust the relevant potentiometer to produce no tone—a result that occurs within a window around the desired value. Although the calibration process is intuitive, the program in Listing 1 visually prompts the technician about which potentiometer to adjust and in which direction to turn it. The technician quickly becomes accustomed to which speed, based on the audio frequency, he or she should adjust the potentiometer to and learns to slow the trimming as the measured value approaches the desired value. The program uses Turbo C++; Listing 1 shows only the relevant sections of code. (DI #2246)

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