EDN Access

Synthesis Shoot-Out at the EDN Corral

Table 2: Accolade PeakFPGA results

Speed emphasis, low effort
  Front-end tools     Back-end (Xilinx Alliance M1) tools              
File
 Compile time1
 Synthesize time2
 Optimize time3
 Place-and-route
time4 		Clock 1 frequency
(MHz)5 		Clock 2 frequency
(MHz)5
CLB flip-flop count 		I/O-buffer flip-
flop count 		Four-LUT count6 Three-LUT count6 Estimated gate count7 CLB count8
BACKFIFO.VHD 00.00:03 00.07:59 00:00:22 00:39:22 Not applicable 2.12 524 0 2875 781 24,076 1494 (47%)
HOST_IF.VHD 00.00:04 00.00:59 00:00:05 00:02:28 16.39 15.45 190 0 591 84 5064 321 (10%)
HOSTFIRD.VHD 00.00:03 00.00:57 00:00:08 00:03:29 14.01 7.59 523 0 930 50 8971 471 (15%)
HOSTFIWR.VHD 00.00:03 00.03:19 00:00:08 00:03:23 8.15 10.55 523 0 882 92 8872 452 (14%)
INTBUFF.VHD 00.00:02 00.00.01 00:00:00 00:00:23 Not applicable Not applicable 0 0 16 0 96 8 (1%)
MEMTOP.VHD 00.00:07 00.00:08 00:00:01 00:00:31 Not applicable 15.91 45 0 79 13 802 43 (1%)
TOPLEVEL.VHD 00.00:04 00.15:42 00:00:48 01:47:44 1.36 0.89 1802 0 6061 1331 54,740 3136 (100%)
X1.VHD 00.00:04 00.00:25 00:00:03 00:01:20 Not applicable Not applicable 0 0 284 76 2354 167 (5%)
X2.VHD 00.00:03 00.00:08 00:00:03 00:01:46 Not applicable Not applicable 0 0 295 27 2892 163 (5%)
BACKFIRM.VHD 00.00:04 00.00:04 00:00:01 00:00:45 Not applicable 10.13 12 0 171 9 5018 95 (3%)
HOFIRDRM.VHD 00.00:03 00.00:03 00:00:00 00:00:34 26.45 2.8 11 0 92 4 4376 47 (1%)
HOFIWRRM.VHD 00.00:03 00.00:03 00:00:00 00:00:36 6.78 11.19 11 0 104 6 4457 55 (1%)
TOPLEVRM.VHD 00.00:04 00.02:03 00:00:13 00:09:42 5.64 2.92 266 0 1666 192 25,165 908 (28%)
Speed emphasis, high effort
File
 Compile time1
 Synthesize time2
 Optimize time3
 Place-and-route
time4 		Clock 1 frequency
(MHz)5 		Clock 2 frequency
(MHz)5 		CLB flip-flop count
 I/O-buffer flip-
flop count 		Four-LUT count6
 Three-LUT count6
 Estimated gate count7
 CLB count8
BACKFIFO.VHD 00:00:03 00:00:38 02:04:45 00:13:05 Not applicable 3.44 524 0 1721 (5) 748 16,974 891 (28%)
HOST_IF.VHD 00:00:04 00:01:06 00:01:29 00:01:39 14.27 25.44 190 0 410 93 4018 227 (7%)
HOSTFIRD.VHD 00:00:03 00:00:12 00:02:49 00:03:28 4.91 3.43 523 0 953 57 9140 480 (15%)
HOSTFIWR.VHD 00:00:03 00:00:13 00:09:01 00:03:23 11.41 15.02 523 0 908 (7) 155 9269 467 (14%)
INTBUFF.VHD 00:00:02 00:00:01 00:00:01 00:00:23 Not applicable Not applicable 0 0 16 0 96 8 (1%)
MEMTOP.VHD 00:00:07 00:00:10 00:00:15 00:00:30 Not applicable 6.68 45 0 73 10 753 39 (1%)
TOPLEVEL.VHD 00:00:04 00:02:31 02:13:04 01:04:15 2.1 1.82 1802 0 4635 (18) 1317 46,013 2456 (78%)
X1.VHD 00:00:04 00:00:05 00:02:10 00:01:10 Not applicable Not applicable 0 0 260 68 2174 154 (4%)
X2.VHD 00:00:03 00:00:06 00:00:20 00:01:48 Not applicable Not applicable 0 0 291 19 2832 162 (5%)
BACKFIRM.VHD 00:00:04 00:00:04 00:00:07 00:00:45 Not applicable 8.44 12 0 173 7 5021 96 (3%)
HOFIRDRM.VHD 00:00:03 00:00:02 00:00:02 00:00:34 36.04 4.18 11 0 90 6 4373 47 (1%)
HOFIWRRM.VHD 00:00:03 00:00:02 00:00:03 00:00:36 6.78 11.19 11 0 104 6 4457 55 (1%)
TOPLEVRM.VHD 00:00:04 00:01:33 00:04:10 00:07:31 4.38 2.97 266 0 1445 72 23,749 792 (25%)
Area emphasis, low effort
File
 Compile time1
 Synthesize time2
 Optimize time3
 Place-and-route
time4 		Clock 1 frequency
(MHz)5 		Clock 2 frequency
(MHz)5 		CLB flip-flop count
 I/O-buffer flip-
flop count 		Four-LUT count6 Three-LUT count6 Estimated gate count7 CLB count8
BACKFIFO.VHD 00:00:03 00:09:05 00:00:25 00:42:48 Not applicable 2.12 524 0 2875 781 24,076 1494 (47%)
HOST_IF.VHD 00:00:04 00:01:12 00:00:06 00:02:25 16.39 15.45 190 0 591 84 5064 321 (10%)
HOSTFIRD.VHD 00:00:03 00:01:05 00:00:08 00:03:23 14.01 7.59 523 0 930 50 8971 471 (15%)
HOSTFIWR.VHD 00:00:03 00:03:53 00:00:09 00:03:20 8.15 10.55 523 0 882 92 8872 452 (14%)
INTBUFF.VHD 00:00:02 00:00:03 00:00:01 00:00:23 Not applicable Not applicable 0 0 16 0 96 8 (1%)
MEMTOP.VHD 00:00:07 00:00:10 00:00:01 00:00:30 Not applicable 15.91 45 0 79 13 802 43 (1%)
TOPLEVEL.VHD 00:00:04 00:15:23 00:00:45 01:47:13 1.29 0.89 1802 0 6061 1331 54,740 3136 (100%)
X1.VHD 00:00:04 00:00:28 00:00:02 00:01:17 Not applicable Not applicable 0 0 284 76 2354 167 (5%)
X2.VHD 00:00:03 00:00:10 00:00:02 00:01:46 Not applicable Not applicable 0 0 295 27 2892 163 (5%)
BACKFIRM.VHD 00:00:04 00:00:04 00:00:01 00:00:46 Not applicable 10.13 12 0 171 9 5018 95 (3%)
HOFIRDRM.VHD 00:00:03 00:00:03 00:00:01 00:00:34 26.45 2.8 11 0 92 4 4376 47 (1%)
HOFIWRRM.VHD 00:00:03 00:00:03 00:00:01 00:00:35 6.78 11.19 11 0 104 6 4457 55 (1%)
TOPLEVRM.VHD 00:00:04 00:01:58 00:00:13 00:09:40 5.64 2.92 266 0 1666 192 25,165 908 (28%)
Area emphasis, high effort
File
 Compile time1
 Synthesize time2
 Optimize time3
 Place-and-route
time4 		Clock 1 frequency
(MHz)5 		Clock 2 frequency
(MHz)5 		CLB flip-flop count
 I/O-buffer flip-
flop count 		Four-LUT count6 Three-LUT count6 Estimated gate count7 CLB count8
BACKFIFO.VHD 00:00:03 00:00:33 01:59:06 00:14:36 Not applicable 3.44 524 0 1721 (5) 748 16,974 891 (28%)
HOST_IF.VHD 00:00:04 00:01:06 00:01:25 00:01:36 14.27 25.44 190 0 410 93 4018 227 (7%)
HOSTFIRD.VHD 00:00:03 00:00:14 00:02:37 00:03:23 4.91 3.43 523 0 953 57 9140 480 (15%)
HOSTFIWR.VHD 00:00:03 00:00:15 00:08:30 00:03:24 11.41 15.02 523 0 908 (7) 155 9269 467 (14%)
INTBUFF.VHD 00:00:02 00:00:01 00:00:01 00:00:23 Not applicable Not applicable 0 0 16 0 96 8 (1%)
MEMTOP.VHD 00:00:07 00:00:08 00:00:09 00:00:30 Not applicable 6.68 45 0 73 10 753 39 (1%)
TOPLEVEL.VHD 00:00:04 00:02:23 02:07:40 01:05:44 2.1 1.82 1802 0 4635 (18) 1317 46,013 2456 (78%)
X1.VHD 00:00:04 00:00:05 00:02:10 00:01:10 Not applicable Not applicable 0 0 260 68 2174 154 (4%)
X2.VHD 00:00:03 00:00:06 00:00:18 00:01:46 Not applicable Not applicable 0 0 291 19 2832 162 (5%)
BACKFIRM.VHD 00:00:04 00:00:03 00:00:07 00:00:45 Not applicable 8.44 12 0 173 7 5021 96 (3%)
HOFIRDRM.VHD 00:00:03 00:00:02 00:00:02 00:00:34 36.04 4.18 11 0 90 6 4373 47 (1%)
HOFIWRRM.VHD 00:00:03 00:00:02 00:00:03 00:00:35 6.78 11.19 11 0 104 6 4457 55 (1%)
TOPLEVRM.VHD 00:00:04 00:01:31 00:04:11 00:07:30 4.38 2.97 266 0 1445 172 23,749 792 (25%)
Notes:

1 All times are in hh:mm:ss (hours, minutes, seconds) format and timed using a stopwatch; LUT=look-up table; CLB=configurable logic block.
2 Includes "analyze" and "elaborate" delays from METAMOR.LOG report.
3 Includes "optimize" and "format" delays from METAMOR.LOG report.
4 Includes "translate," "map," and "place-and-
route" delays from DOS-batch-file TIME captures.
5 Obtained by inserting "NET xxx PERIOD=30;" statements in each .PCF file and then running Xilinx's TRCE utility.
6 Number inside parentheses (if shown) is number of look-up tables used as routing resources.
7 Does not include JTAG logic for I/O buffers.
8 Number inside parentheses is percentage of total available CLBs the design consumes.

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