EDN Access

Synthesis Shoot-Out at the EDN Corral

Table 3: MINC PLSynthesizer results

Speed emphasis, low effort
  Front-end tools   Back-end (Xilinx Alliance M1) tools
File
Compile time1 		Synthesize time2/
optimize time2 		Place-and-route
time (MHz)3 		Clock 1 frequency
(MHz)4 		Clock 2 frequency
(MHz)4 		CLB flip-flop
count 		I/O buffer flip-flop
count 		Four-LUT
count5 		Three-LUT
count5 		Estimated
gate count6 		CLB count7
BACKFIFO.VHD 00:00:04 00:27:25 00:10:55 Not applicable 4.37 524 0 1759 (338) 757 15,076 903 (28%)
HOST_IF.VHD 00:00:05 00:04:42 00:01:46 13.72 20.12 222 0 414 (10) 147 (21) 4323 233 (7%)
HOSTFIRD.VHD 00:00:03 00:03:48 00:01:32 11.94 8.47 523 0 395 361 (256) 5980 391 (12%)
HOSTFIWR.VHD 00:00:03 00:04:18 00:02:03 14.86 28.57 523 0 398 350 (256) 5949 397 (12%)
INTBUFF.VHD 00:00:03 00:00:06 00:00:22 Not applicable Not applicable 0 0 0 0 0 0 (0%)
MEMTOP.VHD 00:00:02 00:00:42 00:01:00 Not applicable 20.33 49 0 75 18 (1) 820 41 (1%)
TOPLEVEL.VHD 00:00:02 01:19:26 00:42:54 11.63 1.53 1838 0 3657 (355) 1774 (525) 36,556 2310 (73%)
X1.VHD 00:00:03 00:03:10 00:01:15 Not applicable Not applicable 0 0 325 103 2413 182 (5%)
X2.VHD 00:00:03 00:02:42 00:00:50 Not applicable Not applicable 0 0 252 84 1890 145 (4%)
BACKFIRM.VHD 00:00:03 00:00:31 00:00:39 Not applicable 12.74 12 0 153 10 4747 78 (2%)
HOFIRDRM.VHD 00:00:03 00:00:32 00:00:32 12.33 5 11 0 91 5 4346 46 (1%)
HOFIWRRM.VHD 00:00:03 00:00:33 00:00:33 12.35 18.8 11 0 107 4 4438 56 (1%)
TOPLEVRM.VHD 00:00:03 00:19:20 00:06:54 7.48 2.45 302 0 1458 (12) 351 (21) 23,205 787 (25%)
Speed emphasis, high effort
File Compile time1 Synthesize time2/optimize time2 Place-and-route time3 Clock 1 frequency (MHz)4 Clock 2 frequency (MHz)4 CLB flip-flop count I/O-buffer flip-flop count Four-LUT count5 Three-LUT count5 Estimated gate count6 CLB count7
BACKFIFO.VHD 00:00:04 00:37:03 00:10:57 Not applicable 4.37 524 0 1759 (338) 757 15,076 903 (28%)
HOST_IF.VHD 00:00:05 00:06:54 00:01:45 9.13 13.03 222 0 417 (29) 167 (19) 4326 243 (7%)
HOSTFIRD.VHD 00:00:03 00:05:18 00:01:30 24.46 15.03 523 0 379 364 (256) 5898 386 (12%)
HOSTFIWR.VHD 00:00:03 00:05:56 00:01:58 10.53 19.04 523 0 396 352 (256) 5946 393 (12%)
INTBUFF.VHD 00:00:03 00:00:06 00:00:22 Not applicable Not applicable 0 0 0 0 0 0 (0%)
MEMTOP.VHD 00:00:02 00:00:42 00:00:59 Not applicable 20.33 490 0 75 18 (1) 820 41 (1%)
TOPLEVEL.VHD 00:00:02 02.31:30 00:43:17 4.54 1.22 1838 0 3832 (59) 1819 (524) 39,589 2410 (76%)
X1.VHD 00:00:03 00:03:16 00:01:15 Not applicable Not applicable 0 0 325 103 2413 182 (5%)
X2.VHD 00:00:03 01.00:22 00:00:50 Not applicable Not applicable 0 0 252 84 1890 145 (4%)
BACKFIRM.VHD 00:00:03 00:00:33 00:00:39 Not applicable 12.74 12 0 153 10 4747 78 (2%)
HOFIRDRM.VHD 00:00:03 00:00:34 00:00:32 12.33 5 11 0 91 5 4346 46 (1%)
HOFIWRRM.VHD 00:00:03 00:00:34 00:00:33 12.35 18.8 11 0 107 4 4438 56 (1%)
TOPLEVRM.VHD 00:00:03 00:50:12 00:06:54 7.48 2.45 302 0 1458 (12) 351 (21) 23,205 787 (25%)
Area emphasis, low effort
File Compile time1 Synthesize time2/optimize time2 Place-and-route time3 Clock 1 frequency (MHz)4 Clock 2 frequency (MHz)4 CLB flip-flop count I/O-buffer flip-flop count Four-LUT count5 Three-LUT count5 Estimated gate count6 CLB count7
BACKFIFO.VHD 00:00:04 00:26:09 00:10:10 Not applicable 5.39 524 0 1751 (336) 718 14,865 895 (28%)
HOST_IF.VHD 00:00:05 00:04:52 00:01:45 12.94 26.63 222 0 337 (9) 133 (20) 3808 200 (6%)
HOSTFIRD.VHD 00:00:03 00:04:00 00:01:37 10.28 10.06 523 0 394 359 (256) 5965 391 (12%)
HOSTFIWR.VHD 00:00:03 00:04:22 00:02:04 8.98 13.69 523 0 398 352 (256) 5938 396 (12%)
INTBUFF.VHD 00:00:03 00:00:08 00:00:22 Not applicable Not applicable 0 0 0 0 0 0 (0%)
MEMTOP.VHD 00:00:02 00:00:50 00:01:01 Not applicable 11.32 49 0 79 15 835 43 (1%)
TOPLEVEL.VHD 00:00:02 01:26:14 00:40:41 4.95 1.64 1838 0 3449 (354) 1677 (526) 34,873 2193 (69%)
X1.VHD 00:00:03 00:02:22 00:01:05 Not applicable Not applicable 0 0 231 81 1750 134 (4%)
X2.VHD 00:00:03 00:02:14 00:00:45 Not applicable Not applicable 0 0 213 40 1458 119 (3%)
BACKFIRM.VHD 00:00:03 00:00:31 00:00:39 Not applicable 13.41 12 0 153 8 4738 79 (2%)
HOFIRDRM.VHD 00:00:03 00:00:32 00:00:31 13.63 3.81 11 0 92 6 4357 47 (1%)
HOFIWRRM.VHD 00:00:03 00:00:32 00:00:34 3.27 24.27 11 0 108 5 4448 55 (1%)
TOPLEVRM.VHD 00:00:03 00:16:28 00:06:39 5.83 2.52 302 0 1243 (9) 284 (20) 21,636 685 (21%)
Area emphasis, high effort
File Compile time1 Synthesize time2/optimize time2 Place-and-route time3 Clock 1 frequency (MHz)4 Clock 2 frequency (MHz)4 CLB flip-flop count I/O-buffer flip-flop count Four-LUT count5 Three-LUT count5 Estimated gate count6 CLB count7
BACKFIFO.VHD 00:00:04 00:37:48 00:10:20 Not applicable 5.39 524 0 1751 (336) 718 14,865 895 (28%)
HOST_IF.VHD 00:00:05 00:07:02 00:01:38 11.67 17.93 222 0 332 (18) 157 (19) 3837 204 (6%)
HOSTFIRD.VHD 00:00:03 00:05:26 00:01:30 12.89 13.67 523 0 382 366 (256) 5925 388 (12%)
HOSTFIWR.VHD 00:00:03 00:06:08 00:02:05 9.41 13.54 523 0 391 353 (256) 5920 393 (12%)
INTBUFF.VHD 00:00:03 00:00:08 00:00:23 Not applicable Not applicable 0 0 0 0 0 0 (0%)
MEMTOP.VHD 00:00:02 00:00:48 00:01:00 Not applicable 11.32 49 0 79 15 835 43 (1%)
TOPLEVEL.VHD 00:00:02 02.53:46 00:40:38 6.68 1.28 1838 0 3437 (354) 1688 (526) 34,851 2192 (69%)
X1.VHD 00:00:03 00:02:24 00:01:07 Not applicable Not applicable 0 0 231 81 1750 134 (4%)
X2.VHD 00:00:03 00:42:38 00:00:45 Not applicable Not applicable 0 0 213 40 1458 119 (3%)
BACKFIRM.VHD 00:00:03 00:00:33 00:00:45 Not applicable 13.41 12 0 153 8 4738 79 (2%)
HOFIRDRM.VHD 00:00:03 00:00:34 00:00:31 13.63 3.81 11 0 92 6 4357 47 (1%)
HOFIWRRM.VHD 00:00:03 00:00:34 00:00:34 3.27 24.27 11 0 108 5 4448 55 (1%)
TOPLEVRM.VHD 00:00:03 00:58:12 00:06:32 5.83 2.52 302 0 1243 (9) 284 (20) 21,636 685 (21%)
Notes:
All times are in hh:mm:ss (hours:minutes:seconds) format and timed using a stopwatch; LUT=look-up table; CLB=configurable logic block.

1 Includes "compiling" delay from PLSxxxx.log report.
2 Includes "compiling," "analyzing," "synthesizing," and "optimizing" delays; measured by noting system clock time when begun and then comparing against .EDN file time stamps on completion.
3 Includes "translate," "map," and "place-and-route" delays from DOS batch file TIME captures.
4 Obtained by inserting "NET xxx PERIOD = 30;" statements in each .PCF file and then running Xilinx’s TRCE utility.
5 Number insideparentheses if shown is the number of LUTs used as routing resources.
6 Does not include JTAG logic for I/O buffers.
7 Number inside parentheses is percentage of totalavailable CLBs the design consumes.

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